Datasheet
MSP430G22x0
SLAS753E –JANUARY 2012–REVISED FEBRUARY 2013
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0x0FFFF to
0x0FFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0x0FFFE) contains 0x0FFFF (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 6. Interrupt Sources
SYSTEM
INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY
INTERRUPT
Power-up
PORIFG
External reset
RSTIFG
Watchdog Timer+ Reset 0xFFFE 31, highest
WDTIFG
Flash key violation
KEYV
(2)
PC out-of-range
(1)
NMI NMIIFG (non)-maskable,
Oscillator fault OFIFG (non)-maskable, 0xFFFC 30
Flash memory access violation ACCVIFG
(2)(3)
(non)-maskable
0xFFFA 29
0xFFF8 28
Comparator_A+
CAIFG
(4)
0xFFF6 27
(MSP430G2210 Only)
Watchdog Timer+ WDTIFG maskable 0xFFF4 26
Timer_A2 TACCR0 CCIFG
(4)
maskable 0xFFF2 25
Timer_A2 TACCR1 CCIFG, TAIFG
(2)(4)
maskable 0xFFF0 24
0xFFEE 23
0xFFEC 22
ADC10 (MSP430G2230 Only) ADC10IFG
(4)
maskable 0xFFEA 21
USI (MSP430G2230 Only) USIIFG, USISTTIFG
(2)(4)
maskable 0xFFE8 20
0xFFE6 19
P1IFG.2, P1IFG.5, P1IFG.6, and
I/O Port P1(four flags) maskable 0xFFE4 18
P1IFG.7
(2)(4)(5)
0xFFE2 17
0xFFE0 16
See
(6)
0xFFDE to 0xFFC0 15 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) All eight interrupt flags P1IFG.0 to P1IFG.7 are implemented while four are connected to pins.
(6) The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
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