Datasheet

MSP430G2x53
MSP430G2x13
SLAS735J –APRIL 2011–REVISED MAY 2013 www.ti.com
Table 2. Terminal Functions
TERMINAL
NO.
I/O DESCRIPTION
NAME
PW20,
PW28 RHB32
N20
P1.0/ General-purpose digital I/O pin
TA0CLK/ Timer0_A, clock signal TACLK input
ACLK/ 2 2 31 I/O ACLK signal output
A0 ADC10 analog input A0
(1)
CA0 Comparator_A+, CA0 input
P1.1/ General-purpose digital I/O pin
TA0.0/ Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit
UCA0RXD/ USCI_A0 UART mode: receive data input
3 3 1 I/O
UCA0SOMI/ USCI_A0 SPI mode: slave data out/master in
A1/ ADC10 analog input A1
(1)
CA1 Comparator_A+, CA1 input
P1.2/ General-purpose digital I/O pin
TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output
UCA0TXD/ USCI_A0 UART mode: transmit data output
4 4 2 I/O
UCA0SIMO/ USCI_A0 SPI mode: slave data in/master out
A2/ ADC10 analog input A2
(1)
CA2 Comparator_A+, CA2 input
P1.3/ General-purpose digital I/O pin
ADC10CLK/ ADC10, conversion clock output
(1)
A3/ ADC10 analog input A3
(1)
5 5 3 I/O
VREF-/VEREF-/ ADC10 negative reference voltage
(1)
CA3/ Comparator_A+, CA3 input
CAOUT Comparator_A+, output
P1.4/ General-purpose digital I/O pin
SMCLK/ SMCLK signal output
UCB0STE/ USCI_B0 slave transmit enable
UCA0CLK/ USCI_A0 clock input/output
6 6 4 I/O
A4/ ADC10 analog input A4
(1)
VREF+/VEREF+/ ADC10 positive reference voltage
(1)
CA4/ Comparator_A+, CA4 input
TCK JTAG test clock, input terminal for device programming and test
P1.5/ General-purpose digital I/O pin
TA0.0/ Timer0_A, compare: Out0 output / BSL receive
UCB0CLK/ USCI_B0 clock input/output
UCA0STE/ 7 7 5 I/O USCI_A0 slave transmit enable
A5/ ADC10 analog input A5
(1)
CA5/ Comparator_A+, CA5 input
TMS JTAG test mode select, input terminal for device programming and test
(1) MSP430G2x53 devices only
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