Datasheet

P1.4/SMCLK/UCB0STE/UCA0CLK/
VREF+*/VEREF+*/CA4/TCKA4*/
Direction
0: Input
1: Output
To Module
SMCLK
PxOUT.y
DVSS
DVCC
1
TAx.y
TAxCLK
Bus
Keeper
EN
1
0
PxIN.y
EN
D
PxSEL.y
PxREN.y
1
0
PxDIR.y
1
0
PxSEL2.y
PxSEL.y
1
0
INCHx = y *
from Comparator
To ADC10 *
To Comparator
From/To ADC10 Ref+ *
PxSEL.y
1
3
2
1
0
PxSEL2.y
From JTAG
To JTAG
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
CAPD.y
or ADC10AE0.y *
* Note: MSP430G2x52 devices only. MSP430G2x12 devices have no ADC10.
From Module
MSP430G2x53
MSP430G2x13
SLAS735J –APRIL 2011–REVISED MAY 2013 www.ti.com
Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger
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