Datasheet

PxDIR.y
From Timer
P1.0/TA0CLK/ACLK/
A0*/CA0
P1.1/TA0.0/UCA0RXD/
UCA0SOMI/A1*/CA1
P1.2/TA0.1/UCA0TXD/
UCA0SIMO/A2*/CA2
From USCI
1
* Note: MSP430G2x53 devices only. MSP430G2x13 devices have no ADC10.
To Module
From Timer
PxOUT.y
DVSS
DVCC
1
TAx.y
TAxCLK
Bus
Keeper
EN
1
0
PxIN.y
EN
D
PxSEL.y
PxREN.y
1
0
PxSEL2.y
1
0
INCHx = y *
To ADC10 *
PxSEL.y
1
3
2
1
0
PxSEL2.y
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxSEL.y
3
2
1
0
PxSEL2.y
From Comparator
To Comparator
CAPD.y
or ADC10AE0.y *
0
MSP430G2x53
MSP430G2x13
SLAS735J –APRIL 2011–REVISED MAY 2013 www.ti.com
PORT SCHEMATICS
Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger
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