Datasheet

MSP430FW42x
www.ti.com SLAS383D –OCTOBER 2003–REVISED JANUARY 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 5. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset WDTIFG
Reset 0FFFEh 15, highest
Watchdog KEYV
(1)
Flash memory
NMI
NMIIFG (Non)maskable
Oscillator Fault
OFIFG (Non)maskable 0FFFCh 14
Flash memory access
ACCVIFG
(1)(2)
(Non)maskable
violation
Timer1_A5 TA1CCR0 CCIFG
(3)
Maskable 0FFFAh 13
TA1CCR1 CCIFG to
Timer1_A5 TA1CCR4 CCIFG, TA1CTL Maskable 0FFF8h 12
TAIFG
(1)(3)
Comparator_A CMPAIFG Maskable 0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
Scan IF SIFIFG0 to SIFIFG6
(1)
Maskable 0FFF2h 9
0FFF0h 8
0FFEEh 7
Timer0_A3 TA0CCR0 CCIFG
(3)
Maskable 0FFECh 6
TA0CCR1 CCIFG,
Timer0_A3 TA0CCR2 CCIFG, Maskable 0FFEAh 5
TA0CTL TAIFG
(1)(2)
I/O port P1
P1IFG.0 to P1IFG.7
(1)(2)
Maskable 0FFE8h 4
(eight flags)
0FFE6h 3
0FFE4h 2
I/O port P2
P2IFG.0 to P2IFG.7
(1)(2)
Maskable 0FFE2h 1
(eight flags)
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
(1) Multiple source flags
(2) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
(3) Interrupt flags are located in the module.
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