Datasheet

MSP430FW42x
www.ti.com SLAS383D –OCTOBER 2003–REVISED JANUARY 2011
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, refer to the MSP430x4xx Family User's Guide (SLAU056).
Oscillator and System Clock
The clock system is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator,
an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+ clock module is
designed to meet the requirements of both low system cost and low power consumption. The FLL+ features a
digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO
frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on
clock source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
Brownout, Supply Voltage Supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and
power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V
CC
may not have
ramped to V
CC(min)
at that time. The user must insure the default FLL+ settings are not changed until V
CC
reaches
V
CC(min)
. If desired, the SVS circuit can be used to determine when V
CC
reaches V
CC(min)
.
Digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD Drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
Watchdog Timer (WDT)
The primary function of the watchdog timer module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as an interval timer and can generate interrupts at
selected time intervals.
Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
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