Datasheet

MSP430FW429, MSP430FW428
MSP430FW427, MSP430FW425, MSP430FW423
www.ti.com SLAS383E –OCTOBER 2003–REVISED DECEMBER 2013
Timer1_A5
Timer1_A5 is a 16-bit timer/counter with five capture/compare registers. Timer1_A5 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A5 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 7. Timer1_A5 Signal Connections
DEVICE INPUT MODULE INPUT MODULE OUTPUT OUTPUT PIN
INPUT PIN NUMBER MODULE BLOCK
SIGNAL NAME SIGNAL NUMBER
32 - P2.5 TA1CLK TACLK
ACLK ACLK
Timer NA
SMCLK SMCLK
32 - P2.5 TA1CLK INCLK
49 - P1.4 TA1.0 CCI0A 49 - P1.4
50 - P1.3 TA1.0 CCI0B
CCR0 TA1.0
DV
SS
GND
DV
CC
V
CC
44 - P2.1 TA1.1 CCI1A 44 - P2.1
CAOUT (internal) CCI1B
CCR1 TA1.1
DV
SS
GND
DV
CC
V
CC
35 - P2.2 TA1.2 CCI2A 35 - P2.2
SIFO0sig (internal) CCI2B
CCR2 TA1.2
DV
SS
GND
DV
CC
V
CC
34 - P2.3 TA1.3 CCI3A 34 - P2.3
SIFO1sig (internal) CCI3B
CCR3 TA1.3
DV
SS
GND
DV
CC
V
CC
33 - P2.4 TA1.4 CCI4A 33 - P2.4
SIFO2sig (internal) CCI4B
CCR4 TA1.4
DV
SS
GND
DV
CC
V
CC
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