Datasheet

P3.4/TB1.1/TB2CLK/SMCLK
P3.5/TB1.2/CDOUT
P3.6/TB2.1/TB1CLK
P3SEL0.x
P3DIR.x
P3IN.x
EN
To modules
From module 1
P3OUT.x
1
0
DVSS
DVCC
1
D
Pad Logic
Bus
Keeper
Direction
0: Input
1: Output
P3REN.x
0 1
0 0
1 0
1 1
P3SEL1.x
0 1
0 0
1 0
1 1
From module 2
DVSS
DVSS
MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
Port P3, P3.4 to P3.6, Input/Output With Schmitt Trigger
Table 50. Port P3 (P3.4 to P3.6) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P3.x) x FUNCTION
P3DIR.x P3SEL1.x P3SEL0.x
P3.4/TB1.1/TB2CLK/SMCLK 4 P3.4 (I/O)
(1)
I: 0; O: 1 0 0
TB1.CCI1B
(1)
0
0 1
TB1.1
(1)
1
TB2CLK
(1)
0
1 1
SMCLK
(1)
1
P3.5/TB1.2/CDOUT 5 P3.5 (I/O)
(1)
I: 0; O: 1 0 0
TB1.CCI2B
(1)
0
0 1
TB1.2
(1)
1
CDOUT
(1)
1 1 1
P3.6/TB2.1/TB1CLK 6 P3.6 (I/O)
(1)
I: 0; O: 1 0 0
TB2.CCI1B
(1)
0
0 1
TB2.1
(1)
1
TB1CLK
(1)
0 1 1
(1) Not available on all devices and package types.
82 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated