Datasheet

MSP430FR573x
MSP430FR572x
www.ti.com SLAS639H –JULY 2011–REVISED SEPTEMBER 2013
10-Bit ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
AV
CC
and DV
CC
are connected together,
AV
CC
Analog supply voltage AV
SS
and DV
SS
are connected together, 2.0 3.6 V
V
(AVSS)
= V
(DVSS)
= 0 V
V
(Ax)
Analog input voltage range All ADC10 pins 0 AV
CC
V
Operating supply current into f
ADC10CLK
= 5 MHz, ADC10ON = 1, 2 V 90 140
I
ADC10_A
AVCC terminal, reference REFON = 0, SHT0 = 0, SHT1 = 0, µA
3 V 100 160
current not included ADC10DIV = 0
Only one terminal Ax can be selected at one
C
I
Input capacitance time from the pad to the ADC10_A capacitor 2.2 V 6 8 pF
array including wiring and pad
R
I
Input MUX ON resistance AV
CC
≥ 2 V, 0 V ≤ V
Ax
≤ AV
CC
36 kΩ
10-Bit ADC, Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
For specified performance of ADC10 linearity 2 V to
f
ADC10CLK
0.45 5 5.5 MHz
parameters 3.6 V
Internal ADC10 oscillator 2 V to
f
ADC10OSC
ADC10DIV = 0, f
ADC10CLK
= f
ADC10OSC
4.5 4.5 5.5 MHz
(MODOSC) 3.6 V
REFON = 0, Internal oscillator,
2 V to
12 ADC10CLK cycles, 10-bit mode, 2.18 2.67
3.6 V
f
ADC10OSC
= 4.5 MHz to 5.5 MHz
t
CONVERT
Conversion time µs
External f
ADC10CLK
from ACLK, MCLK, or SMCLK, 2 V to
(1)
ADC10SSEL ≠ 0 3.6 V
The error in a conversion started after t
ADC10ON
is
Turn on settling time of
t
ADC10ON
less than ±0.5 LSB, 100 ns
the ADC
Reference and input signal already settled
R
S
= 1000 Ω, R
I
= 36000 Ω, C
I
= 3.5 pF, 2 V 1.5
t
Sample
Sampling time Approximately eight Tau (τ) are required to get an µs
3 V 2.0
error of less than ±0.5 LSB
(1) 12 × ADC10DIV × 1/f
ADC10CLK
10-Bit ADC, Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
1.4 V ≤ (V
eREF+
– V
REF–
/V
eREF–
)min ≤ 1.6 V -1.4 1.4
Integral 2 V to
E
I
LSB
linearity error 3.6 V
1.6 V < (V
eREF+
– V
REF–
/V
eREF–
)min ≤ V
AVCC
-1.1 1.1
Differential 2 V to
E
D
(V
eREF+
– V
REF–
/V
eREF–
)min ≤ (V
eREF+
– V
REF–
/V
eREF–
) -1 1 LSB
linearity error 3.6 V
2 V to
E
O
Offset error (V
eREF+
– V
REF–
/V
eREF–
)min ≤ (V
eREF+
– V
REF–
/V
eREF–
) -6.5 6.5 mV
3.6 V
Gain error, external 2 V to
(V
eREF+
– V
REF–
/V
eREF–
)min ≤ (V
eREF+
– V
REF–
/V
eREF–
) -1.2 1.2 LSB
reference 3.6 V
E
G
Gain error, internal
-4 4 %
reference
(1)
Total unadjusted
2 V to
error, external (V
eREF+
– V
REF–
/V
eREF–
)min ≤ (V
eREF+
– V
REF–
/V
eREF–
) -2 2 LSB
3.6 V
reference
E
T
Total unadjusted
error, internal -4 4 %
reference
(1)
(1) Error is dominated by the internal reference.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 65