Datasheet

MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
2 V 7
t
STE,LEAD
STE lead time, STE active to clock ns
3 V 7
2 V 0
t
STE,LAG
STE lag time, Last clock to STE inactive ns
3 V 0
2 V 65
t
STE,ACC
STE access time, STE active to SOMI data out ns
3 V 40
2 V 40
STE disable time, STE inactive to SOMI high
t
STE,DIS
ns
impedance
3 V 35
2 V 2
t
SU,SI
SIMO input data setup time ns
3 V 2
2 V 5
t
HD,SI
SIMO input data hold time ns
3 V 5
2 V 30
UCLK edge to SOMI valid,
t
VALID,SO
SOMI output data valid time
(2)
ns
C
L
= 20 pF
3 V 30
2 V 4
t
HD,SO
SOMI output data hold time
(3)
C
L
= 20 pF ns
3 V 4
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(eUSCI)
, t
SU,MI(Master)
+ t
VALID,SO(eUSCI)
).
For the master's parameters t
SU,MI(Master)
and t
VALID,MO(Master)
see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 9 and Figure 10.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 9
and Figure 10.
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