Datasheet

MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
eUSCI
eUSCI input clock frequency f
SYSTEM
MHz
Duty cycle = 50% ± 10%
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
UCSTEM = 0,
2 V, 3 V 1
UCMODEx = 01 or 10
UCxCLK
t
STE,LEAD
STE lead time, STE active to clock
cycles
UCSTEM = 1,
2 V, 3 V 1
UCMODEx = 01 or 10
UCSTEM = 0,
2 V, 3 V 1
UCMODEx = 01 or 10
STE lag time, Last clock to STE UCxCLK
t
STE,LAG
inactive cycles
UCSTEM = 1,
2 V, 3 V 1
UCMODEx = 01 or 10
UCSTEM = 0,
2 V, 3 V 55
UCMODEx = 01 or 10
STE access time, STE active to SIMO
t
STE,ACC
ns
data out
UCSTEM = 1,
2 V, 3 V 35
UCMODEx = 01 or 10
UCSTEM = 0,
2 V, 3 V 40
UCMODEx = 01 or 10
STE disable time, STE inactive to
t
STE,DIS
ns
SIMO high impedance
UCSTEM = 1,
2 V, 3 V 30
UCMODEx = 01 or 10
2 V 35
t
SU,MI
SOMI input data setup time ns
3 V 35
2 V 0
t
HD,MI
SOMI input data hold time ns
3 V 0
2 V 30
UCLK edge to SIMO valid,
t
VALID,MO
SIMO output data valid time
(2)
ns
C
L
= 20 pF
3 V 30
2 V 0
t
HD,MO
SIMO output data hold time
(3)
C
L
= 20 pF ns
3 V 0
(1) f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
= max(t
VALID,MO(eUSCI)
+ t
SU,SI(Slave)
, t
SU,MI(eUSCI)
+ t
VALID,SO(Slave)
).
For the slave's parameters t
SU,SI(Slave)
and t
VALID,SO(Slave)
see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 7 and Figure 8.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 7
and Figure 8.
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