Datasheet

MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
TB0, TB1, TB2
TB0, TB1, and TB2 are 16-bit timers/counters (Timer_B type) with three capture/compare registers each. Each
can support multiple capture/compares, PWM outputs, and interval timing. Each has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 13. TB0 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
RHA RGE, YQD DA PW RHA RGE, YQD DA PW
SIGNAL SIGNAL SIGNAL SIGNAL
13-P2.0,
21-P2.0 23-P2.0 19-P2.0 TB0CLK TBCLK
E5‑P2.0
ACLK
ACLK
(internal)
Timer N/A N/A
SMCLK
SMCLK
(internal)
13-P2.0,
21-P2.0 23-P2.0 19-P2.0 TB0CLK TBCLK
E5‑P2.0
14-P2.1, 14-P2.1,
22-P2.1 24-P2.1 20-P2.1 TB0.0 CCI0A 22-P2.1 24-P2.1 20-P2.1
D3‑P2.1 D3‑P2.1
17-P2.5 N/A 19-P2.5 15-P2.5 TB0.0 CCI0B 17-P2.5 N/A 19-P2.5 15-P2.5
ADC10 ADC10 ADC10 ADC10
CCR0 TB0 TB0.0
(internal)
(1)
(internal)
(1)
(internal)
(1)
(internal)
(1)
DV
SS
GND
ADC10SHSx ADC10SHSx ADC10SHSx ADC10SHSx
= {2} = {2} = {2} = {2}
DV
CC
V
CC
5-P1.4, 5-P1.4,
9-P1.4 13-P1.4 9-P1.4 TB0.1 CCI1A 9-P1.4 13-P1.4 9-P1.4
B4‑P1.4 B4‑P1.4
ADC10 ADC10 ADC10 ADC10
CDOUT (internal)
(1)
(internal)
(1)
(internal)
(1)
(internal)
(1)
CCI1B
CCR1 TB1 TB0.1
(internal) ADC10SHSx ADC10SHSx ADC10SHSx ADC10SHSx
= {3} = {3} = {3} = {3}
DV
SS
GND
DV
CC
V
CC
6‑P1.5, A5- 6-P1.5,
10-P1.5 14-P1.5 19-P1.5 TB0.2 CCI2A 10-P1.5 14-P1.5 19-P1.5
P1.5 A5‑P1.5
ACLK
CCI2B
CCR2 TB2 TB0.2
(internal)
DV
SS
GND
DV
CC
V
CC
(1) Only on devices with ADC
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