Datasheet

MSP430FR573x
MSP430FR572x
www.ti.com SLAS639H –JULY 2011–REVISED SEPTEMBER 2013
Table 1. Family Members
(1)(2)
(continued)
eUSCI
System
Channel
FRAM SRAM
Channel
Device Clock ADC10_B Comp_D Timer_A
(3)
Timer_B
(4)
I/O Package
A:
(KB) (KB)
B:
(MHz)
UART,
SPI, I
2
C
IrDA, SPI
32 RHA
MSP430FR5733 8 1 24 16 ch. 3, 3 3, 3, 3 2 1
30 DA
10 ch. 17 RGE
MSP430FR5732 8 1 24 3, 3 3 1 1
12 ch. 21 PW
32 RHA
12 ext,
MSP430FR5731 4 1 24 16 ch. 3, 3 3, 3, 3 2 1
2 int ch.
30 DA
6 ext, 2 int
10 ch. 17 RGE
ch.
MSP430FR5730 4 1 24 3, 3 3 1 1
8 ext, 2 int
12 ch. 21 PW
ch.
32 RHA
12 ext,
MSP430FR5729 16 1 8 16 ch. 3, 3 3, 3, 3 2 1
2 int ch.
30 DA
6 ext, 2 int
10 ch. 17 RGE
ch.
MSP430FR5728 16 1 8 3, 3 3 1 1
8 ext, 2 int
12 ch. 21 PW
ch.
32 RHA
MSP430FR5727 16 1 8 16 ch. 3, 3 3, 3, 3 2 1
30 DA
10 ch. 17 RGE
MSP430FR5726 16 1 8 3, 3 3 1 1
12 ch. 21 PW
32 RHA
12 ext,
MSP430FR5725 8 1 8 16 ch. 3, 3 3, 3, 3 2 1
2 int ch.
30 DA
6 ext, 2 int
10 ch. 17 RGE
ch.
MSP430FR5724 8 1 8 3, 3 3 1 1
8 ext, 2 int
12 ch. 21 PW
ch.
32 RHA
MSP430FR5723 8 1 8 16 ch. 3, 3 3, 3, 3 2 1
30 DA
10 ch. 17 RGE
MSP430FR5722 8 1 8 3, 3 3 1 1
12 ch. 21 PW
32 RHA
12 ext,
MSP430FR5721 4 1 8 16 ch. 3, 3 3, 3, 3 2 1
2 int ch.
30 DA
6 ext, 2 int
10 ch. 17 RGE
ch.
MSP430FR5720 4 1 8 3, 3 3 1 1
8 ext, 2 int
12 ch. 21 PW
ch.
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