Datasheet
MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013
Table 4. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
UCA1RXIFG, UCA1TXIFG (SPI mode)
UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG,
eUSCI_A1 Receive and Transmit Maskable 0FFE6h 51
UXA1TXIFG (UART mode)
(UCA1IV)
(1) (3)
DMA0IFG, DMA1IFG, DMA2IFG
DMA Maskable 0FFE4h 50
(DMAIV)
(1) (3)
TA1 TA1CCR0 CCIFG0
(3)
Maskable 0FFE2h 49
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1 TA1IFG Maskable 0FFE0h 48
(TA1IV)
(1) (3)
P1IFG.0 to P1IFG.7
I/O Port P1 Maskable 0FFDEh 47
(P1IV)
(1) (3)
TB1 TB1CCR0 CCIFG0
(3)
Maskable 0FFDCh 46
TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2,
TB1 TB1IFG Maskable 0FFDAh 45
(TB1IV)
(1) (3)
P2IFG.0 to P2IFG.7
I/O Port P2 Maskable 0FFD8h 44
(P2IV)
(1) (3)
TB2 TB2CCR0 CCIFG0
(3)
Maskable 0FFD6h 43
TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2,
TB2 TB2IFG Maskable 0FFD4h 42
(TB2IV)
(1) (3)
P3IFG.0 to P3IFG.7
I/O Port P3 Maskable 0FFD2h 41
(P3IV)
(5) (6)
P4IFG.0 to P4IFG.2
I/O Port P4 Maskable 0FFD0h 40
(P4IV)
(5) (6)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_B RT0PSIFG, RT1PSIFG, RTCOFIFG Maskable 0FFCEh 39
(RTCIV)
(5) (6)
0FFCCh 38
Reserved Reserved
(7)
⋮ ⋮
0FF80h 0, lowest
(5) Multiple source flags
(6) Interrupt flags are located in the module.
(7) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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