Datasheet

PJ.3/TCK/CD9
PJSEL0.x
PJDIR.x
PJIN.x
EN
To modules
and JTAG
PJOUT.x
1
0
DVSS
DVCC
1
D
Pad Logic
Bus
Keeper
Direction
0: Input
1: Output
PJREN.x
0 1
0 0
1 0
1 1
PJSEL1.x
0 1
0 0
1 0
1 1
DVSS
DVSS
0
1
0
1
JTAG enable
From JTAG
From JTAG
To Comparator
From Comparator
CDPD.x
0
1
From JTAG
DVSS
PJSEL0.x
PJDIR.x
PJIN.x
EN
To modules
and JTAG
PJOUT.x
1
0
DVSS
DVCC
1
D
Pad Logic
Bus
Keeper
Direction
0: Input
1: Output
PJREN.x
0 1
0 0
1 0
1 1
PJSEL1.x
0 1
0 0
1 0
1 1
DVSS
DVSS
0
1
0
1
JTAG enable
From JTAG
From JTAG
To Comparator
From Comparator
CDPD.x
0
1
From JTAG
From module 1
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
Port J, J.0 to J.3 JTAG pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or
Output
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