Datasheet

P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
P2SEL0.x
P2DIR.x
P2IN.x
EN
To modules
From module 1
P2OUT.x
1
0
DVSS
DVCC
1
D
Pad Logic
Bus
Keeper
Direction
0: Input
1: Output
P2REN.x
0 1
0 0
1 0
1 1
P2SEL1.x
0 1
0 0
1 0
1 1
From module 2
From module 2
From module 3
DVSS
MSP430FR573x
MSP430FR572x
www.ti.com SLAS639H –JULY 2011–REVISED SEPTEMBER 2013
Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
Table 45. Port P2 (P2.0 to P2.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x) x FUNCTION
P2DIR.x P2SEL1.x P2SEL0.x
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK 0 P2.0 (I/O) I: 0; O: 1 0 0
TB2.CCI0A
(1)
0
0 1
TB2.0
(1)
1
UCA0TXD/UCA0SIMO X
(2)
1 0
TB0CLK 0
1 1
ACLK 1
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0 1 P2.1 (I/O) I: 0; O: 1 0 0
TB2.CCI1A
(1)
0
0 1
TB2.1
(1)
1
UCA0RXD/UCA0SOMI X
(2)
1 0
TB0.CCI0A 0
1 1
TB0.0 1
P2.2/TB2.2/UCB0CLK/TB1.0 2 P2.2 (I/O) I: 0; O: 1 0 0
TB2.CCI2A
(1)
0
0 1
TB2.2
(1)
1
UCB0CLK X
(3)
1 0
TB1.CCI0A
(1)
0
1 1
TB1.0
(1)
1
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_A0 module.
(3) Direction controlled by eUSCI_B0 module.
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