Datasheet

MSP430FR573x
MSP430FR572x
www.ti.com SLAS639H –JULY 2011–REVISED SEPTEMBER 2013
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK 8
f
TA
Timer_A input clock frequency External: TACLK 2 V, 3 V MHz
24
(1)
Duty cycle = 50% ± 10%
All capture inputs, Minimum pulse
t
TA,cap
Timer_A capture timing 2 V, 3 V 20 ns
duration required for capture
(1) MSP430FR573x devices only
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK 8
f
TB
Timer_B input clock frequency External: TBCLK 2 V, 3 V MHz
24
(1)
Duty cycle = 50% ± 10%
All capture inputs, Minimum pulse
t
TB,cap
Timer_B capture timing 2 V, 3 V 20 ns
duration required for capture
(1) MSP430FR573x devices only
eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
eUSCI
eUSCI input clock frequency External: UCLK f
SYSTEM
MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
f
BITCLK
5 MHz
(equals baud rate in MBaud)
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
UCGLITx = 0 5 15 20
UCGLITx = 1 20 45 60
t
t
UART receive deglitch time
(1)
2 V, 3 V ns
UCGLITx = 2 35 80 120
UCGLITx = 3 50 110 180
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
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