Datasheet

MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at V
CC
to V
SS
–0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE)
(2)
–0.3 V to V
CC
+ 0.3 V
Diode current at any device pin ±2 mA
Storage temperature range, T
stg
(3) (4) (5)
-55°C to 125°C
Maximum junction temperature, T
J
95°C
(1) Stresses beyond those listed under "absolute maximum ratings " may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
. V
CORE
is for internal device use only. No external DC loading or voltage should be applied.
(3) Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, T
stg
.
(4) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(5) Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
Recommended Operating Conditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25°C (unless otherwise noted)
MIN NOM MAX UNIT
V
CC
Supply voltage during program execution and FRAM programming (AVCC = DVCC)
(1)
2.0 3.6 V
V
SS
Supply voltage (AVSS = DVSS) 0 V
T
A
Operating free-air temperature I version -40 85 °C
T
J
Operating junction temperature I version -40 85 °C
C
VCORE
Required capacitor at VCORE
(2)
470 nF
C
VCC
/
Capacitor ratio of VCC to VCORE 10
C
VCORE
No FRAM wait states
(4)
,
0 8.0
2 V ≤ V
CC
≤ 3.6 V
With FRAM wait states
(4)
,
f
SYSTEM
Processor frequency (maximum MCLK frequency)
(3)
MHz
NACCESS = {2},
0 24.0
NPRECHG = {1},
2 V ≤ V
CC
≤ 3.6 V
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) A capacitor tolerance of ±20% or better is required.
(3) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(4) When using manual wait state control, see the MSP430FR57xx Family User's Guide (SLAU272) for recommended settings for common
system frequencies.
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