Datasheet

MSP430FR573x
MSP430FR572x
www.ti.com SLAS639H –JULY 2011–REVISED SEPTEMBER 2013
Short-Form Description
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Operating Modes
The MSP430 has one active mode and seven software-selectable low-power modes of operation. An interrupt
event can wake up the device from low-power modes LPM0 through LPM4, service the request, and restore back
to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the
core supply to minimize power consumption.
The following eight operating modes can be configured by software:
– CPU is disabled
• Active mode (AM)
– ACLK active, MCLK and SMCLK disabled
– All clocks are active
– DCO disabled
• Low-power mode 0 (LPM0)
– Complete data retention
– CPU is disabled
• Low-power mode 4 (LPM4)
– ACLK active, MCLK disabled, SMCLK
– CPU is disabled
optionally active
– ACLK, MCLK, SMCLK disabled
– Complete data retention
– Complete data retention
• Low-power mode 1 (LPM1)
• Low-power mode 3.5 (LPM3.5)
– CPU is disabled
– RTC operation
– ACLK active, MCLK disabled, SMCLK
– Internal regulator disabled
optionally active
– No data retention
– DCO disabled
– I/O pad state retention
– Complete data retention
– Wake up from RST, general-purpose I/O, RTC
• Low-power mode 2 (LPM2)
events
– CPU is disabled
• Low-power mode 4.5 (LPM4.5)
– ACLK active, MCLK disabled, SMCLK
– Internal regulator disabled
optionally active
– No data retention
– DCO disabled
– I/O pad state retention
– Complete data retention
– Wake up from RST and general-purpose I/O
• Low-power mode 3 (LPM3)
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