Datasheet

MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
APPLICATIONS
• Home Automation
• Security
• Sensor Management
• Data Acquisition
CAUTION These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such
as those experienced during reflow or hand soldering. See Absolute Maximum Ratings for more information.
CAUTION System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical
overstress or disturb of data or code memory. See the application report MSP430™ System-Level ESD Considerations
(SLAA530) for more information.
DESCRIPTION
The Texas Instruments MSP430FR57xx family of ultralow-power microcontrollers consists of multiple devices
that feature embedded FRAM nonvolatile memory, ultralow-power 16-bit MSP430™ CPU, and different
peripherals targeted for various applications. The architecture, FRAM, and peripherals, combined with seven low-
power modes, are optimized to achieve extended battery life in portable and wireless sensing applications.
FRAM is a new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the
stability and reliability of flash, all at lower total power consumption. Peripherals include 10-bit analog-to-digital
converter (ADC), 16-channel comparator with voltage reference generation and hysteresis capabilities, three
enhanced serial channels capable of I
2
C, SPI, or UART protocols, an internal DMA, a hardware multiplier, a real-
time clock (RTC), five 16-bit timers, and more. Table 1 summarizes the available family members.
Table 1. Family Members
(1)(2)
eUSCI
System
Channel
FRAM SRAM
Channel
Device Clock ADC10_B Comp_D Timer_A
(3)
Timer_B
(4)
I/O Package
A:
(KB) (KB)
B:
(MHz)
UART,
SPI, I
2
C
IrDA, SPI
32 RHA
12 ext,
MSP430FR5739 16 1 24 16 ch. 3, 3 3, 3, 3 2 1
2 int ch.
30 DA
6 ext, 2 int
10 ch. 17 RGE
ch.
8 ext, 2 int
MSP430FR5738 16 1 24 12 ch. 3, 3 3 1 1 21 PW
ch.
6 ext, 2 int
10 ch. 17 YQD
(5)
ch.
32 RHA
MSP430FR5737 16 1 24 16 ch. 3, 3 3, 3, 3 2 1
30 DA
10 ch. 17 RGE
MSP430FR5736 16 1 24 3, 3 3 1 1
12 ch. 21 PW
32 RHA
12 ext,
MSP430FR5735 8 1 24 16 ch. 3, 3 3, 3, 3 2 1
2 int ch.
30 DA
6 ext, 2 int
10 ch. 17 RGE
ch.
MSP430FR5734 8 1 24 3, 3 3 1 1
8 ext, 2 int
12 ch. 21 PW
ch.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(5) Product Preview
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