Datasheet

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
56
POST OFFICE BOX 655303  DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
f
USCI
USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50%  10%
f
SYSTEM
MHz
fmax,
BITCLK
Maximum BITCLK clock frequency
(equals baudrate in MBaud) (see
Note 1)
2.2V /3 V 2 MHz
t
U
A
RT receive de
g
litch time
2.2 V 50 150 ns
t

U
A
R
T
r
e
c
e
i
v
e
d
e
g
l
i
t
c
h
t
i
m
e
(see Note NO TAG)
3V 50 100 ns
NOTES: 1. The DCO wake -up time must be considered in LPM3/4 for baudrates above 1 MHz.
2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
USCI (SPI master mode) (see Figure 31 and Figure 32)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
f
USCI
USCI input clock frequency
SMCLK, ACLKm
Duty cycle = 50%  10%
f
SYSTEM
MHz
t
S
O
M
I
i
n
p
u
t
d
a
t
a
s
e
t
u
p
t
i
m
e
2.2 V 110 ns
t
SU,MI
SOMI input data setup time
3V 75 ns
t
S
O
M
I
i
n
p
u
t
d
a
t
a
h
o
l
d
t
i
m
e
2.2 V 0 ns
t
HD,MI
SOMI input data hold time
3V 0 ns
t
S
I
M
O
o
u
t
p
u
t
d
a
t
a
v
a
l
i
d
t
i
m
e
U
C
L
K
e
d
g
e
t
o
S
I
M
O
v
a
l
i
d
C
2
0
p
F
2.2 V 30 ns
t
VALID,MO
SIMO output data valid time UCLK edge to SIMO valid, C
L
=20pF
3V 20 ns
NOTE: f
UCxCLK
=
1
2t
LO∕HI
with t
LO∕HI
≥ max(t
VALID,MO(USCI)
+ t
SU,SI(Slave),
t
SU,MI(USCI)
+ t
VALID,SO(Slave)
).
For the slave’s parameters t
SU,SI(Slave)
and t
VALID,SO(Slave)
refer to the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 33 and Figure 34)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
t
STE,LEAD
STE lead time
STE low to clock
2.2 V/3 V 50 ns
t
STE,LAG
STE lag time
Last clock to STE high
2.2 V/3 V 10 ns
t
STE,ACC
STE access time
STE low to SOMI data out
2.2 V/3 V 50 ns
t
STE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V 50 ns
t
S
I
M
O
i
n
p
t
d
a
t
a
s
e
t
p
t
i
m
e
2.2 V 20 ns
t
SU,SI
SIMO input data setup time
3V 15 ns
t
S
I
M
O
i
n
p
t
d
a
t
a
h
o
l
d
t
i
m
e
2.2 V 10 ns
t
HD,SI
SIMO input data hold time
3V 10 ns
t
S
O
M
I
o
t
p
t
d
a
t
a
a
l
i
d
t
i
m
e
UCLK ed
g
etoSOMIvalid,
2.2 V 75 110 ns
t
VALID,SO
SOMI output data valid time
U
C
L
K
e
d
g
e
t
o
S
O
M
I
v
a
l
i
d
,
C
L
=20pF
3V 50 75 ns
NOTE: f
UCxCLK
=
1
2t
LO∕HI
with t
LO∕HI
≥ max(t
VALID,MO(Master)
+ t
SU,SI(USCI),
t
SU,MI(Master)
+ t
VALID,SO(USCI)
).
For the master’s parameters t
SU,MI(Master)
and t
VALID,MO(Master)
refer to the SPI parameters of the attached master.