Datasheet
Table Of Contents
- features
- description
- AVAILABLE OPTIONS
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430xG461xIPZ
- pin designation, MSP430xG461xIZQW (top view)
- functional block diagram
- Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers (SFRs)
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- DMA controller
- oscillator and system clock
- brownout, supply voltage supervisor
- brownout, supply voltage supervisor
- digital I/O
- Basic Timer1 and Real-Time Clock
- LCD_A drive with regulated charge pump
- watchdog timer (WDT+)
- universal serial communication interface (USCI)
- USART1
- hardware multiplier
- Timer_A3
- Timer_B7
- Comparator_A
- ADC12
- DAC12
- OA
- peripheral file map
- absolute maximum ratings over operating free-air temperature
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs -- Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
- inputs Px.x, TAx, TBx
- leakage current -- Ports P1 to P10
- outputs -- Ports P1 to P10
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USCI (UART mode)
- USCI (SPI master mode)
- USCI (SPI slave mode)
- USCI (I2C mode)
- USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4)
- operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6)
- flash memory (MSP430FG461x devices only)
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- Port P1, P1.0 to P1.5, input/output with Schmitt trigger
- Port P1 (P1.0 to P1.5) pin functions
- Port P1, P1.6, P1.7, input/output with Schmitt trigger
- Port P1 (P1.6 and P1.7) pin functions
- port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt trigger
- Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
- port P2, P2.4 to P2.5, input/output with Schmitt trigger
- Port P2 (P2.4 and P2.5) pin functions
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- Port P3 (P3.0 to P3.3) pin functions
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- Port P3 (P3.4 to P3.7) pin functions
- port P4, P4.0 to P4.1, input/output with Schmitt trigger
- Port P4 (P4.0 to P4.1) pin functions
- port P4, P4.2 to P4.7, input/output with Schmitt trigger
- Port P4 (P4.2 to P4.5) pin functions
- port P5, P5.0, input/output with Schmitt trigger
- Port P5 (P5.0) pin functions
- port P5, P5.1, input/output with Schmitt trigger
- Port P5 (P5.1) pin functions
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- Port P5 (P5.2 to P5.4) pin functions
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- Port P5 (P5.5 to P5.7) pin functions
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger
- Port P6 (P6.0, P6.2, and P6.4) pin functions
- port P6, P6.1, P6.3, and P6.5 input/output with Schmitt trigger
- Port P6 (P6.1, P6.3, and P6.5) pin functions
- port P6, P6.6, input/output with Schmitt trigger
- Port P6 (P6.6) pin functions
- port P6, P6.7, input/output with Schmitt trigger
- Port P6 (P6.7) pin functions
- port P7, P7.0 to P7.3, input/output with Schmitt trigger
- Port P7 (P7.0 to P7.1) pin functions
- port P7, P7.4 to P7.7, input/output with Schmitt trigger
- Port P7 (P7.4 to P7.5) pin functions
- port P8, P8.0 to P8.7, input/output with Schmitt trigger
- Port P8 (P8.0 to P8.1) pin functions
- Port P8 (P8.6 to P8.7) pin functions
- port P9, P9.0 to P9.7, input/output with Schmitt trigger
- Port P9 (P9.0 to P9.1) pin functions
- port P10, P10.0 to P10.5, input/output with Schmitt trigger
- Port P10 (P10.0 to P10.1) pin functions
- port P10, P10.6, input/output with Schmitt trigger
- Port P10 (P10.6) pin functions
- port P10, P10.7, input/output with Schmitt trigger
- Port P10 (P10.7) pin functions
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
flash memory (MSP430FG461x devices only)
PARAMETER
TEST
CONDITIONS
V
CC
MIN TYP MAX UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage 2.7 3.6 V
f
FTG
Flash Timing Generator frequency 257 476 kHz
I
PGM
Supply current from DV
CC
during program 2.7 V/ 3.6 V 3 5 mA
I
ERASE
Supply current from DV
CC
during erase See Note 3 2.7 V/ 3.6 V 3 7 mA
I
GMERASE
Supply current from DV
CC
during global
mass erase
See Note 4 2.7 V/ 3.6 V 6 14 mA
t
CPT
Cumulative program time See Note 1 2.7 V/ 3.6 V 10 ms
t
CMErase
Cumulative mass erase time 2.7 V/ 3.6 V 20 ms
Program/Erase endurance 10
4
10
5
cycles
t
Retention
Data retention duration T
J
= 25°C 100 years
t
Word
Word or byte program time 30
t
Block,
0
Block program time for 1
st
byte or word 25
t
Block,
1-63
Block program time for each additional byte
or word
SNt2
18
t
t
Block,
End
Block program end-sequence wait time
See Note 2
6
t
FTG
t
Mass
Erase
Mass erase time 10593
t
Global
Mass
Erase
Global mass erase time 10593
t
Seg
Erase
Segment erase time 4819
NOTES: 1. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write
feature is used.
2. These values are hardwired into the Flash Controller’s state machine (t
FTG
= 1/f
FTG
).
3. Lower 64-KB or upper 64-KB Flash memory erased.
4. All Flash memory erased.
JTAG interface
PARAMETER
TEST
CONDITIONS
V
CC
MIN TYP MAX UNIT
f
TCK input frequency
See Note 1
2.2 V 0 5 MHz
f
TCK
TCK input frequency See Note 1
3 V 0 10 MHz
R
Internal
Internal pull-up resistance on TMS, TCK, TDI/TCLK See Note 2 2.2 V/ 3 V 25 60 90 kΩ
NOTES: 1. f
TCK
may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER
TEST
CONDITIONS
V
CC
MIN TYP MAX UNIT
V
CC(FB)
Supply voltage during fuse-blow condition T
A
= 25°C 2.5 V
V
FB
Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V
I
FB
Supply current into TDI/TCLK during fuse blow 100 mA
t
FB
Time to blow fuse 1 ms
NOTE 1: Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.