Datasheet
Table Of Contents
- features
- description
- AVAILABLE OPTIONS
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430xG461xIPZ
- pin designation, MSP430xG461xIZQW (top view)
- functional block diagram
- Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers (SFRs)
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- DMA controller
- oscillator and system clock
- brownout, supply voltage supervisor
- brownout, supply voltage supervisor
- digital I/O
- Basic Timer1 and Real-Time Clock
- LCD_A drive with regulated charge pump
- watchdog timer (WDT+)
- universal serial communication interface (USCI)
- USART1
- hardware multiplier
- Timer_A3
- Timer_B7
- Comparator_A
- ADC12
- DAC12
- OA
- peripheral file map
- absolute maximum ratings over operating free-air temperature
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs -- Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
- inputs Px.x, TAx, TBx
- leakage current -- Ports P1 to P10
- outputs -- Ports P1 to P10
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USCI (UART mode)
- USCI (SPI master mode)
- USCI (SPI slave mode)
- USCI (I2C mode)
- USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4)
- operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6)
- flash memory (MSP430FG461x devices only)
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- Port P1, P1.0 to P1.5, input/output with Schmitt trigger
- Port P1 (P1.0 to P1.5) pin functions
- Port P1, P1.6, P1.7, input/output with Schmitt trigger
- Port P1 (P1.6 and P1.7) pin functions
- port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt trigger
- Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
- port P2, P2.4 to P2.5, input/output with Schmitt trigger
- Port P2 (P2.4 and P2.5) pin functions
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- Port P3 (P3.0 to P3.3) pin functions
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- Port P3 (P3.4 to P3.7) pin functions
- port P4, P4.0 to P4.1, input/output with Schmitt trigger
- Port P4 (P4.0 to P4.1) pin functions
- port P4, P4.2 to P4.7, input/output with Schmitt trigger
- Port P4 (P4.2 to P4.5) pin functions
- port P5, P5.0, input/output with Schmitt trigger
- Port P5 (P5.0) pin functions
- port P5, P5.1, input/output with Schmitt trigger
- Port P5 (P5.1) pin functions
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- Port P5 (P5.2 to P5.4) pin functions
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- Port P5 (P5.5 to P5.7) pin functions
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger
- Port P6 (P6.0, P6.2, and P6.4) pin functions
- port P6, P6.1, P6.3, and P6.5 input/output with Schmitt trigger
- Port P6 (P6.1, P6.3, and P6.5) pin functions
- port P6, P6.6, input/output with Schmitt trigger
- Port P6 (P6.6) pin functions
- port P6, P6.7, input/output with Schmitt trigger
- Port P6 (P6.7) pin functions
- port P7, P7.0 to P7.3, input/output with Schmitt trigger
- Port P7 (P7.0 to P7.1) pin functions
- port P7, P7.4 to P7.7, input/output with Schmitt trigger
- Port P7 (P7.4 to P7.5) pin functions
- port P8, P8.0 to P8.7, input/output with Schmitt trigger
- Port P8 (P8.0 to P8.1) pin functions
- Port P8 (P8.6 to P8.7) pin functions
- port P9, P9.0 to P9.7, input/output with Schmitt trigger
- Port P9 (P9.0 to P9.1) pin functions
- port P10, P10.0 to P10.5, input/output with Schmitt trigger
- Port P10 (P10.0 to P10.1) pin functions
- port P10, P10.6, input/output with Schmitt trigger
- Port P10 (P10.6) pin functions
- port P10, P10.7, input/output with Schmitt trigger
- Port P10 (P10.7) pin functions
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OSCCAPx = 0h, V
CC
= 2.2 V / 3 V 0
C
Inte
g
rated input capacitance
OSCCAPx = 1h, V
CC
= 2.2 V / 3 V 10
pF
C
XIN
Integrated
input
capacitance
(see Note 4)
OSCCAPx = 2h, V
CC
= 2.2 V / 3 V 14
pF
OSCCAPx = 3h, V
CC
= 2.2 V / 3 V 18
OSCCAPx = 0h, V
CC
= 2.2 V / 3 V 0
C
Inte
g
rated output capacitance
OSCCAPx = 1h, V
CC
= 2.2 V / 3 V 10
pF
C
XOUT
Integrated
output
capacitance
(see Note 4)
OSCCAPx = 2h, V
CC
= 2.2 V / 3 V 14
pF
OSCCAPx = 3h, V
CC
= 2.2 V / 3 V 18
V
IL
Input levels at XIN
V 2 2 V/3 V (see Note 3)
V
SS
0.2×V
CC
V
V
IH
Input levels at XIN V
CC
= 2.2 V/3 V (see Note 3)
0.8×V
CC
V
CC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(C
XIN
xC
XOUT
) / (C
XIN
+ C
XOUT
). This is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep the trace between the device and the crystal as short as possible.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
C
XT2IN
Integrated input capacitance V
CC
= 2.2 V/3 V 2 pF
C
XT2OUT
Integrated output capacitance V
CC
= 2.2 V/3 V 2 pF
V
IL
Input levels at XT2IN
V
CC
= 2 2 V/3 V (see Note 2)
V
SS
0.2 × V
CC
V
V
IH
Input levels at XT2IN V
CC
= 2.2 V/3 V (see Note 2)
0.8 × V
CC
V
CC
V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.