Datasheet
Table Of Contents
- features
- description
- AVAILABLE OPTIONS
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430xG461xIPZ
- pin designation, MSP430xG461xIZQW (top view)
- functional block diagram
- Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers (SFRs)
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- DMA controller
- oscillator and system clock
- brownout, supply voltage supervisor
- brownout, supply voltage supervisor
- digital I/O
- Basic Timer1 and Real-Time Clock
- LCD_A drive with regulated charge pump
- watchdog timer (WDT+)
- universal serial communication interface (USCI)
- USART1
- hardware multiplier
- Timer_A3
- Timer_B7
- Comparator_A
- ADC12
- DAC12
- OA
- peripheral file map
- absolute maximum ratings over operating free-air temperature
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs -- Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
- inputs Px.x, TAx, TBx
- leakage current -- Ports P1 to P10
- outputs -- Ports P1 to P10
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USCI (UART mode)
- USCI (SPI master mode)
- USCI (SPI slave mode)
- USCI (I2C mode)
- USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4)
- operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6)
- flash memory (MSP430FG461x devices only)
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- Port P1, P1.0 to P1.5, input/output with Schmitt trigger
- Port P1 (P1.0 to P1.5) pin functions
- Port P1, P1.6, P1.7, input/output with Schmitt trigger
- Port P1 (P1.6 and P1.7) pin functions
- port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt trigger
- Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
- port P2, P2.4 to P2.5, input/output with Schmitt trigger
- Port P2 (P2.4 and P2.5) pin functions
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- Port P3 (P3.0 to P3.3) pin functions
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- Port P3 (P3.4 to P3.7) pin functions
- port P4, P4.0 to P4.1, input/output with Schmitt trigger
- Port P4 (P4.0 to P4.1) pin functions
- port P4, P4.2 to P4.7, input/output with Schmitt trigger
- Port P4 (P4.2 to P4.5) pin functions
- port P5, P5.0, input/output with Schmitt trigger
- Port P5 (P5.0) pin functions
- port P5, P5.1, input/output with Schmitt trigger
- Port P5 (P5.1) pin functions
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- Port P5 (P5.2 to P5.4) pin functions
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- Port P5 (P5.5 to P5.7) pin functions
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger
- Port P6 (P6.0, P6.2, and P6.4) pin functions
- port P6, P6.1, P6.3, and P6.5 input/output with Schmitt trigger
- Port P6 (P6.1, P6.3, and P6.5) pin functions
- port P6, P6.6, input/output with Schmitt trigger
- Port P6 (P6.6) pin functions
- port P6, P6.7, input/output with Schmitt trigger
- Port P6 (P6.7) pin functions
- port P7, P7.0 to P7.3, input/output with Schmitt trigger
- Port P7 (P7.0 to P7.1) pin functions
- port P7, P7.4 to P7.7, input/output with Schmitt trigger
- Port P7 (P7.4 to P7.5) pin functions
- port P8, P8.0 to P8.7, input/output with Schmitt trigger
- Port P8 (P8.0 to P8.1) pin functions
- Port P8 (P8.6 to P8.7) pin functions
- port P9, P9.0 to P9.7, input/output with Schmitt trigger
- Port P9 (P9.0 to P9.1) pin functions
- port P10, P10.0 to P10.5, input/output with Schmitt trigger
- Port P10 (P10.0 to P10.1) pin functions
- port P10, P10.6, input/output with Schmitt trigger
- Port P10 (P10.6) pin functions
- port P10, P10.7, input/output with Schmitt trigger
- Port P10 (P10.7) pin functions
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
f
(DCOCLK)
N
(DCO)
=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0 2.2 V/3 V 1 MHz
f
FN 8 FN 4 FN 3 FN 2 0 ; DCOPLUS 1
2.2 V 0.3 0.65 1.25
MHz
f
(DCO=2)
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
3 V 0.3 0.7 1.3
MHz
f
FN 8 FN 4 FN 3 FN 2 0; DCOPLUS 1
2.2 V 2.5 5.6 10.5
MHz
f
(DCO=27)
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1
3 V 2.7 6.1 11.3
MHz
f
FN 8 FN 4 FN 3 0 FN 2 1; DCOPLUS 1
2.2 V 0.7 1.3 2.3
MHz
f
(DCO=2)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
3 V 0.8 1.5 2.5
MHz
f
FN 8 FN 4 FN 3 0 FN 2 1; DCOPLUS 1
2.2 V 5.7 10.8 18
MHz
f
(DCO=27)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
3 V 6.5 12.1 20
MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x; DCOPLUS 1
2.2 V 1.2 2 3
MHz
f
(DCO=2)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
3 V 1.3 2.2 3.5
MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x; DCOPLUS 1
2.2 V 9 15.5 25
MHz
f
(DCO=27)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
3 V 10.3 17.9 28.5
MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x; DCOPLUS 1
2.2 V 1.8 2.8 4.2
MHz
f
(DCO=2)
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
3 V 2.1 3.4 5.2
MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x; DCOPLUS 1
2.2 V 13.5 21.5 33
MHz
f
(DCO=27)
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1
3 V 16 26.6 41
MHz
f
FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS 1
2.2 V 2.8 4.2 6.2
MHz
f
(DCO=2)
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
3 V 4.2 6.3 9.2
MHz
f
FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS 1
2.2 V 21 32 46
MHz
f
(DCO=27)
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1
3 V 30 46 70
MHz
S
Step size between adjacent DCO taps:
1 < TAP ≤ 20 1.06 1.11
S
n
Step
size
between
adjacent
DCO
taps:
S
n
= f
DCO(Tap
n+1)
/ f
DCO(Tap
n)
(see Figure 16 for taps 21 to 27)
TAP = 27 1.07 1.17
D
Temperature drift, N
(
D
CO)
= 01Eh, FN_8=FN_4=FN_3=FN_2=0
2.2 V –0.2 –0.3 –0.4
%/_C
D
t
Temperature
drift
,
N
(DCO)
=
01Eh
,
FN
_
8=FN
_
4=FN
_
3=FN
_
2=0
D = 2; DCOPLUS = 0
3 V –0.2 –0.3 –0.4
%/_C
D
V
Drift with V
CC
variation, N
(DCO)
= 01Eh, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0
0 5 15 %/V
T
A
− °CV
CC
− V
f
(DCO)
f
(DCO20
5
C)
f
(DCO)
f
(DCO3V)
1.8 3.02.4 3.6
1.0
20 6040 85
1.0
0−20−400
Figure 15. DCO Frequency vs Supply Voltage V
CC
and vs Ambient Temperature