Datasheet
Table Of Contents
- features
- description
- AVAILABLE OPTIONS
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430xG461xIPZ
- pin designation, MSP430xG461xIZQW (top view)
- functional block diagram
- Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers (SFRs)
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- DMA controller
- oscillator and system clock
- brownout, supply voltage supervisor
- brownout, supply voltage supervisor
- digital I/O
- Basic Timer1 and Real-Time Clock
- LCD_A drive with regulated charge pump
- watchdog timer (WDT+)
- universal serial communication interface (USCI)
- USART1
- hardware multiplier
- Timer_A3
- Timer_B7
- Comparator_A
- ADC12
- DAC12
- OA
- peripheral file map
- absolute maximum ratings over operating free-air temperature
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs -- Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
- inputs Px.x, TAx, TBx
- leakage current -- Ports P1 to P10
- outputs -- Ports P1 to P10
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USCI (UART mode)
- USCI (SPI master mode)
- USCI (SPI slave mode)
- USCI (I2C mode)
- USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4)
- operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6)
- flash memory (MSP430FG461x devices only)
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- Port P1, P1.0 to P1.5, input/output with Schmitt trigger
- Port P1 (P1.0 to P1.5) pin functions
- Port P1, P1.6, P1.7, input/output with Schmitt trigger
- Port P1 (P1.6 and P1.7) pin functions
- port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt trigger
- Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
- port P2, P2.4 to P2.5, input/output with Schmitt trigger
- Port P2 (P2.4 and P2.5) pin functions
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- Port P3 (P3.0 to P3.3) pin functions
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- Port P3 (P3.4 to P3.7) pin functions
- port P4, P4.0 to P4.1, input/output with Schmitt trigger
- Port P4 (P4.0 to P4.1) pin functions
- port P4, P4.2 to P4.7, input/output with Schmitt trigger
- Port P4 (P4.2 to P4.5) pin functions
- port P5, P5.0, input/output with Schmitt trigger
- Port P5 (P5.0) pin functions
- port P5, P5.1, input/output with Schmitt trigger
- Port P5 (P5.1) pin functions
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- Port P5 (P5.2 to P5.4) pin functions
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- Port P5 (P5.5 to P5.7) pin functions
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger
- Port P6 (P6.0, P6.2, and P6.4) pin functions
- port P6, P6.1, P6.3, and P6.5 input/output with Schmitt trigger
- Port P6 (P6.1, P6.3, and P6.5) pin functions
- port P6, P6.6, input/output with Schmitt trigger
- Port P6 (P6.6) pin functions
- port P6, P6.7, input/output with Schmitt trigger
- Port P6 (P6.7) pin functions
- port P7, P7.0 to P7.3, input/output with Schmitt trigger
- Port P7 (P7.0 to P7.1) pin functions
- port P7, P7.4 to P7.7, input/output with Schmitt trigger
- Port P7 (P7.4 to P7.5) pin functions
- port P8, P8.0 to P8.7, input/output with Schmitt trigger
- Port P8 (P8.0 to P8.1) pin functions
- Port P8 (P8.6 to P8.7) pin functions
- port P9, P9.0 to P9.7, input/output with Schmitt trigger
- Port P9 (P9.0 to P9.1) pin functions
- port P10, P10.0 to P10.5, input/output with Schmitt trigger
- Port P10 (P10.0 to P10.1) pin functions
- port P10, P10.6, input/output with Schmitt trigger
- Port P10 (P10.6) pin functions
- port P10, P10.7, input/output with Schmitt trigger
- Port P10 (P10.7) pin functions
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader security key is
provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid
password is supplied. The BSL is optional for ROM-based devices. For complete description of the features of
the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature
number SLAA089.
BSLKEY DESCRIPTION
00000h Erasure of flash disabled if an invalid password is supplied
0AA55h BSL disabled
any other value BSL enabled
BSL FUNCTION PZ/ZQW PACKAGE PINS
Data Transmit 87/A7 − P1.0
Data Receive 86/E7 − P1.1
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.