Datasheet
Table Of Contents
- features
- description
- AVAILABLE OPTIONS
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430xG461xIPZ
- pin designation, MSP430xG461xIZQW (top view)
- functional block diagram
- Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers (SFRs)
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- DMA controller
- oscillator and system clock
- brownout, supply voltage supervisor
- brownout, supply voltage supervisor
- digital I/O
- Basic Timer1 and Real-Time Clock
- LCD_A drive with regulated charge pump
- watchdog timer (WDT+)
- universal serial communication interface (USCI)
- USART1
- hardware multiplier
- Timer_A3
- Timer_B7
- Comparator_A
- ADC12
- DAC12
- OA
- peripheral file map
- absolute maximum ratings over operating free-air temperature
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs -- Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
- inputs Px.x, TAx, TBx
- leakage current -- Ports P1 to P10
- outputs -- Ports P1 to P10
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USCI (UART mode)
- USCI (SPI master mode)
- USCI (SPI slave mode)
- USCI (I2C mode)
- USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4)
- operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6)
- flash memory (MSP430FG461x devices only)
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- Port P1, P1.0 to P1.5, input/output with Schmitt trigger
- Port P1 (P1.0 to P1.5) pin functions
- Port P1, P1.6, P1.7, input/output with Schmitt trigger
- Port P1 (P1.6 and P1.7) pin functions
- port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt trigger
- Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
- port P2, P2.4 to P2.5, input/output with Schmitt trigger
- Port P2 (P2.4 and P2.5) pin functions
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- Port P3 (P3.0 to P3.3) pin functions
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- Port P3 (P3.4 to P3.7) pin functions
- port P4, P4.0 to P4.1, input/output with Schmitt trigger
- Port P4 (P4.0 to P4.1) pin functions
- port P4, P4.2 to P4.7, input/output with Schmitt trigger
- Port P4 (P4.2 to P4.5) pin functions
- port P5, P5.0, input/output with Schmitt trigger
- Port P5 (P5.0) pin functions
- port P5, P5.1, input/output with Schmitt trigger
- Port P5 (P5.1) pin functions
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- Port P5 (P5.2 to P5.4) pin functions
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- Port P5 (P5.5 to P5.7) pin functions
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger
- Port P6 (P6.0, P6.2, and P6.4) pin functions
- port P6, P6.1, P6.3, and P6.5 input/output with Schmitt trigger
- Port P6 (P6.1, P6.3, and P6.5) pin functions
- port P6, P6.6, input/output with Schmitt trigger
- Port P6 (P6.6) pin functions
- port P6, P6.7, input/output with Schmitt trigger
- Port P6 (P6.7) pin functions
- port P7, P7.0 to P7.3, input/output with Schmitt trigger
- Port P7 (P7.0 to P7.1) pin functions
- port P7, P7.4 to P7.7, input/output with Schmitt trigger
- Port P7 (P7.4 to P7.5) pin functions
- port P8, P8.0 to P8.7, input/output with Schmitt trigger
- Port P8 (P8.0 to P8.1) pin functions
- Port P8 (P8.6 to P8.7) pin functions
- port P9, P9.0 to P9.7, input/output with Schmitt trigger
- Port P9 (P9.0 to P9.1) pin functions
- port P10, P10.0 to P10.5, input/output with Schmitt trigger
- Port P10 (P10.0 to P10.1) pin functions
- port P10, P10.6, input/output with Schmitt trigger
- Port P10 (P10.6) pin functions
- port P10, P10.7, input/output with Schmitt trigger
- Port P10 (P10.7) pin functions
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History

MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 26)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Resolution (12-bit Monotonic) 12 bits
INL
Integral nonlinearity
V
ref
= 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±20
±80
LSB
INL
Integral
nonlinearity
(see Note 1)
V
ref
= 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
±2.0 ±8.0 LSB
DNL
Differential nonlinearity
V
ref
= 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±04
±10
LSB
DNL
Differential
nonlinearity
(see Note 1)
V
ref
= 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
±0.4 ±1.0 LSB
Offset voltage without
calibration
V
ref
= 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±21
E
O
calibration
(see Notes 1, 2)
V
ref
= 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
±21
mV
Offset voltage with
calibration
V
ref
= 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±25
mV
calibration
(see Notes 1, 2)
V
ref
= 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
±2.5
d
E(O)
/d
T
Offset error
temperature coefficient
(see Note 1)
2.2 V/3 V ±30 μV/°C
E
Gain error (see Note 1)
V
REF
= 1.5 V 2.2 V
±350
% FSR
E
G
Gain error (see Note 1)
V
REF
= 2.5 V 3 V
±3.50 % FSR
d
E(G)
/d
T
Gain temperature
coefficient (see Note 1)
2.2 V/3 V 10
ppm of
FSR/°C
Time for offset calibration
DAC12AMPx = 2 100
t
Offset_Cal
Time for offset calibration
(see Note 3)
DAC12AMPx = 3,5
2.2 V/3 V
32
ms
t
Offset
_
Cal
(see Note 3)
DAC12AMPx = 4,6,7
2.2
V/3
V
6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. V
DAC12_xOUT
= E
O
+ (1 + E
G
) * (V
eREF+
/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during
calibration may effect accuracy and is not recommended.
Positive
Negative
V
R+
Gain Error
Offset Error
DAC Code
DAC V
OUT
Ideal transfer
function
R
Load
=
AV
CC
C
Load
= 100pF
2
DAC Output
Figure 26. Linearity Test Load Conditions and Gain/Offset Definition