Datasheet

MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380C − APRIL 2004 − REVISED MARCH 2011
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
OA2 Operational Amplifier 2 control register 1
Operational Amplifier 2 control register 0
OA2CTL1
OA2CTL0
0C5h
0C4h
OA1 Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 0
OA1CTL1
OA1CTL0
0C3h
0C2h
OA0 Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 0
OA0CTL1
OA0CTL0
0C1h
0C0h
LCD LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0A4h
:
0A0h
09Fh
:
091h
090h
ADC12
ADC memory-control register 15 ADC12MCTL15 08Fh
(Memory control
registers require byte
ADC memory-control register 14 ADC12MCTL14 08Eh
registers require byte
access)
ADC memory-control register 13 ADC12MCTL13 08Dh
access
)
ADC memory-control register 12 ADC12MCTL12 08Ch
ADC memory-control register 11 ADC12MCTL11 08Bh
ADC memory-control register 10 ADC12MCTL10 08Ah
ADC memory-control register 9 ADC12MCTL9 089h
ADC memory-control register 8 ADC12MCTL8 088h
ADC memory-control register 7 ADC12MCTL7 087h
ADC memory-control register 6 ADC12MCTL6 086h
ADC memory-control register 5 ADC12MCTL5 085h
ADC memory-control register 4 ADC12MCTL4 084h
ADC memory-control register 3 ADC12MCTL3 083h
ADC memory-control register 2 ADC12MCTL2 082h
ADC memory-control register 1 ADC12MCTL1 081h
ADC memory-control register 0 ADC12MCTL0 080h
USART0
Transmit buffer U0TXBUF 077h
(UART or SPI mode)
Receive buffer U0RXBUF 076h
Baud rate U0BR1 075h
Baud rate U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
Comparator_A
Comparator_A port disable CAPD 05Bh
p
_
Comparator_A control 2 CACTL2 05Ah
Comparator_A control 1 CACTL1 059h
BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 056h