Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 16-Bit 8 MHz I/O number 48

MSP430FG43x

MIXED SIGNAL MICROCONTROLLER

SLAS380C − APRIL 2004 − REVISED MARCH 2011

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

D Low Supply-Voltage Range, 1.8 V to 3.6 V

D Ultralow-Power Consumption:

− Active Mode: 300 μA at 1 MHz, 2.2 V

− Standby Mode: 1.1 μA

− Off Mode (RAM Retention): 0.1 μA

D Five Power Saving Modes

D Wake-Up From Standby Mode in Less

Than 6 μs

D 16-Bit RISC Architecture,

125-ns Instruction Cycle Time

D Single-Channel Internal DMA

D 12-Bit A/D Converter With Internal

Reference, Sample-and-Hold and

Autoscan Feature

D Three Configurable Operational Amplifiers

D Dual 12-Bit D/A Converters With

Synchronization

D 16-Bit Timer_A With Three

Capture/Compare Registers

D 16-Bit Timer_B With Three

Capture/Compare-With-Shadow Registers

D On-Chip Comparator

D Serial Communication Interface (USART),

Select Asynchronous UART or

Synchronous SPI by Software

D Brownout Detector

D Supply Voltage Supervisor/Monitor With

Programmable Level Detection

D Bootstrap Loader

D Serial Onboard Programming,

No External Programming Voltage Needed

Programmable Code Protection by Security

Fuse

D Integrated LCD Driver for Up to

128 Segments

D Family Members Include:

− MSP430FG437:

32KB+256B Flash Memory,

1KB RAM

− MSP430FG438:

48KB+256B Flash Memory,

2KB RAM

− MSP430FG439:

60KB+256B Flash Memory,

2KB RAM

D For Complete Module Descriptions, See

The MSP430x4xx Family User’s Guide,

Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code

efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less

than 6μs.

The MSP430FG43x series are microcontroller configurations with two 16-bit timers, a high performance 12-bit

A/D converter, dual 12-bit D/A converters, three configurable operational amplifiers, one universal

synchronous/asynchronous communication interface (USART), DMA, 48 I/O pins, and a liquid crystal display

(LCD) driver.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote

controls, thermostats, digital timers, hand-held meters, etc.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range

from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage

because very small parametric changes could cause the device not to meet its published specifications. These devices have limited

built-in ESD protection.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (76 pages)

PAGE 1
MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption: D D D D D D D D D D D D Brownout Detector D Supply Voltage Supervisor/Monitor With − Active Mode: 300 μA at 1 MHz, 2.2 V − Standby Mode: 1.1 μA − Off Mode (RAM Retention): 0.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 80-PIN QFP (PN) MSP430FG437IPN MSP430FG438IPN MSP430FG439IPN −40°C to 85°C P6.2/A2/OA0I1 P6.1/A1/OA0O P6.0/A0/OA0I0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT AVCC DVSS1 AVSS PN PACKAGE (TOP VIEW) P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 MSP430FG43x functional block diagram XIN XT2IN XT2OUT DVCC1/2 DVSS1/2 XOUT AVCC AVSS P1 P2 P4 P3 8 8 P6 P5 8 8 8 8 ACLK Oscillator FLL+ Flash SMCLK 60KB 48KB 32KB MCLK 8 MHz CPU incl. 16 Registers Emulation Module ADC12 DAC12 Port 1 Port 2 2KB 1KB 12-Biit 12 Channels <10μs Conv.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 MSP430FG43x Terminal Functions TERMINAL PN NAME NO. DESCRIPTION I/O DVCC1 1 P6.3/A3/OA1I1/OA1O 2 I/O General-purpose digital I/O / analog input a3—12-bit ADC / OA1 output and/or input multiplexer on +terminal and −terminal P6.4/A4/OA1I0 3 I/O General-purpose digital I/O / analog input a4—12-bit ADC / OA1 input multiplexer on +terminal and −terminal P6.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 MSP430FG43x Terminal Functions (Continued) TERMINAL PN NAME NO. DESCRIPTION I/O P3.3/UCLK0/S28 40 I/O General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI mode, clock o/p—USART0/SPI mode / LCD segment output 28 P3.2/SOMI0/S29 41 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 29 P3.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 MSP430FG43x Terminal Functions (Continued) TERMINAL PN NAME NO. DESCRIPTION I/O RST/NMI 74 I P6.0/A0/OA0I0 75 I/O General-purpose digital I/O / analog input a0 − 12-bit ADC / OA0 input multiplexer on +terminal and − terminal P6.1/A1/OA0O 76 I/O General-purpose digital I/O / analog input a1 − 12-bit ADC / OA0 output P6.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 special function registers The MSP430 special function registers(SFR) are located in the lowest address space, and are organized as byte mode registers. SFRs should be accessed with byte instructions. interrupt enable 1 and 2 7 Address 0h 6 UTXIE0 rw–0 URXIE0 rw–0 5 4 ACCVIE NMIIE rw–0 3 2 1 OFIE rw–0 rw–0 Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 module enable registers 1 and 2 7 UTXE0 Address 04h rw–0 6 URXE0 USPIE0 5 4 3 1 0 2 1 0 rw–0 URXE0: USART0: UART mode receive enable UTXE0: USART0: UART mode transmit enable USPIE0: USART0: SPI mode transmit and receive enable Address 2 7 6 5 4 3 05h Legend: rw: rw–0,1: rw–(0,1): Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset or Set by PUC. Bit Can Be Read and Written.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, Literature Number SLAU056. DMA controller The DMA controller allows movement of data from one memory address to another without CPU intervention.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 LCD drive The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. OA The MSP430FG43x has three configurable low-current general-purpose operational amplifiers.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 timer_B3 Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog timer control WDTCTL 0120h Timer_B3 _ Capture/compare register 2 TBCCR2 0196h Capture/compare register 1 TBCCR1 0194h Capture/compare register 0 TBCCR0 0192h Timer_B register TBR 0190h Capture/compare control 2 TBCCTL2 0186h Capture/compare control 1 TBCCTL1 0184h Capture/compare control 0 TBCCTL0 0182h Timer_B control TBCTL 0180h
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH WORD ACCESS (CONTINUED) ADC12 Conversion memory 15 ADC12MEM15 015Eh See also Peripherals with Byte y Access Conversion memory 14 ADC12MEM14 015Ch Conversion memory 13 ADC12MEM13 015Ah Conversion memory 12 ADC12MEM12 0158h Conversion memory 11 ADC12MEM11 0156h Conversion memory 10 ADC12MEM10 0154h Conversion memory 9 ADC12MEM9 0152h Conversion memory 8
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS OA2 Operational Amplifier 2 control register 1 Operational Amplifier 2 control register 0 OA2CTL1 OA2CTL0 0C5h 0C4h OA1 Operational Amplifier 1 control register 1 Operational Amplifier 1 control register 0 OA1CTL1 OA1CTL0 0C3h 0C2h OA0 Operational Amplifier 0 control register 1 Operational Amplifier 0 control register 0 OA0CTL1 OA0CTL0 0C1h 0C0h LCD L
PAGE 19
MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) FLL+ Clock FLL+ Control 1 FLL_CTL1 054h FLL+ Control 0 FLL_CTL0 053h System clock frequency control SCFQCTL 052h System clock frequency integrator SCFI1 051h System clock frequency integrator SCFI0 050h Basic Timer1 BT counter 2 BT counter 1 BT control BTCNT2 BTCNT1 BTCTL 047h 046h 040h Port P6 Port P6 selection P6SEL 037h Port
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Diode current at any device terminal . . .
PAGE 21
MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AVCC + DVCC1/2 excluding external current PARAMETER TEST CONDITIONS Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz XTS_FLL=0, SELM=(0,1) TA = −40°C 40°C to 85°C I(LPM0) Low power mode, (LPM0) Low-power (see Note 1 and Note 4) TA = −40°C 40°C to 85°C I(LPM2) Low-power mode
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI PARAMETER VIT+ Positive going input threshold voltage Positive-going VIT− Negative going input threshold voltage Negative-going Vhys Input voltage hysteresis (VIT+ − VIT−) TEST CONDITIONS MIN TYP MAX VCC
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P3, P4, P5, and P6 PARAMETER VOH VOL High level output voltage High-level Low level output voltage Low-level TEST CONDITIONS MIN TYP MAX IOH(max) = −1.5 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC IOH(max) = −6 mA, VCC = 2.2 V, See Note 2 VCC−0.6 VCC IOH(max) = −1.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P3, P4, P5, and P6 (continued) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 25 TA = 25°C VCC = 2.2 V P2.
PAGE 25
MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) wake-up LPM3 PARAMETER TEST CONDITIONS MIN TYP MAX f = 1 MHz td(LPM3) f = 2 MHz Delay time UNIT 6 6 VCC = 2.2 V/3 V f = 3 MHz μs 6 RAM PARAMETER TEST CONDITIONS VRAMh MIN CPU halted (see Note 1) TYP MAX 1.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS I(CC) CAON 1 CARSEL=0, CAON=1, CARSEL 0 CAREF=0 CAREF 0 I(Refladder/RefDiode) CAON=1, CARSEL=0, CAREF=1/2/3, No load at P1.6/CA0 P1 6/CA0 and P1.7/CA1 V(Ref025) V(Ref050) Voltage @ 0.25 V V CC TYP MAX VCC = 2.2 V 25 40 VCC = 3 V 45 60 VCC = 2.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 typical characteristics REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 650 650 VCC = 2.2 V 600 VREF − Reference Voltage − mV VREF − Reference Voltage − mV VCC = 3 V Typical 550 500 450 400 −45 −25 −5 15 35 55 75 600 Typical 550 500 450 400 −45 95 −25 TA − Free-Air Temperature − °C Figure 6.
PAGE 28
MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) POR/brownout reset (BOR) (see Note 1) PARAMETER TEST CONDITIONS MIN TYP td(BOR) dVCC/dt ≤ 3 V/s (see Figure 10) VCC(start) V(B_IT−) Vhys(B_IT−) t(reset) UNIT 2000 μs 0.
PAGE 29
MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 typical characteristics VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 tf = tr 0 0.001 1 1000 tf tr tpw − Pulse Width − μs tpw − Pulse Width − μs Figure 12.
PAGE 30
MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 typical characteristics Software Sets VLD>0: SVS is Active VCC V(SVS_IT−) V(SVSstart) Vhys(SVS_IT−) Vhys(B_IT−) V(B_IT−) VCC(start) BrownOut Region Brownout Region Brownout 1 0 td(BOR) SVSOut t d(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT−) 1 0 td(SVSon) Set POR 1 td(SVSR) undefined 0 Figure 13. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop VCC(drop) VCC(drop) − V 1.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) DCO PARAMETER VCC f(DCOCLK) N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0, fCrystal = 32.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 Sn - Stepsize Ratio between DCO Taps electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 1.17 ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ Max 1.11 1.07 1.06 Min 1 20 27 DCO Tap Figure 16.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) crystal oscillator, LFXT1 oscillator (see Notes 1 and 2) PARAMETER CXIN CXOUT Integrated input capacitance (see Note 4) Integrated output capacitance (see Note 4) TEST CONDITIONS MIN TYP OSCCAPx = 0h, VCC = 2.2 V / 3 V 0 OSCCAPx = 1h, VCC = 2.2 V / 3 V 10 OSCCAPx = 2h, VCC = 2.2 V / 3 V 14 OSCCAPx = 3h, VCC = 2.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS MIN AVCC Analog supply voltage AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V V(P6.x/Ax) Analog input voltage range (see Note 2) All external Ax terminals.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, built-in reference PARAMETER Positive built in reference built-in voltage output VREF+ AVCC(min) AVCC minimum voltage, Positive built-in built in reference active IVREF+ Load current out of VREF+ terminal Load current regulation Load-current VREF+ terminal IL(VREF)+ TEST CONDITIONS REF2_5V = 1
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 From Power Supply DVCC1/2 + − 10 μ F DVSS1/2 100 nF AVCC + − 10 μ F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 100 nF VREF+ or VeREF+ + − Apply External Reference 10 μ F 100 nF VREF−/VeREF− + − 10 μ F MSP430FG43x AVSS 100 nF Figure 19.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, timing parameters PARAMETER TEST CONDITIONS fADC12CLK fADC12OSC tCONVERT Internal ADC12 oscillator Conversion time MIN NOM MAX UNIT For specified performance of ADC12 linearity parameters VCC = 2.2V/3 V 0.45 5 6.3 MHz ADC12DIV=0, fADC12CLK=fADC12OSC VCC = 2.2 V/ 3 V 3.7 5 6.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, temperature sensor and built-in VMID PARAMETER TEST CONDITIONS VCC MIN NOM MAX Operating supply current into AVCC terminal (see Note 1) REFON = 0, INCH = 0Ah, ADC12ON=NA, TA = 25_C 2.2 V 40 120 ISENSOR 3V 60 160 VSENSOR (see Note 2) ADC12ON = 1, INCH = 0Ah, TA = 0°C 2.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (see Figure 21) PARAMETER TEST CONDITIONS Resolution INL DNL EO MIN (12-bit Monotonic) Integral nonlinearity (see Note 1) Differential nonlinearity (see Note 1) Offset voltage w/o calibration (see Notes 1, 2) Offset voltage with calibration (see Notes 1, 2) dE(O)/dT
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, linearity specifications (continued) TYPICAL INL ERROR vs DIGITAL INPUT DATA INL − Integral Nonlinearity Error − LSB 4 VCC = 2.2 V, VREF = 1.
PAGE 41
MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit DAC, output specifications PARAMETER VO TEST CONDITIONS Output voltage range (see Note 1, Figure 24) CL(DAC12) Max DAC12 load capacitance IL(DAC12) Max DAC12 load current RO/P(DAC12) Output Resistance (see Figure 24) VCC MIN TYP MAX No Load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AM
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit DAC, reference input specifications PARAMETER TYP MAX DAC12IR=0, (see Notes 1 and 2) TEST CONDITIONS 2.2V/3V AVCC/3 AVCC+0.2 DAC12IR=1, (see Notes 3 and 4) 2.2V/3V AVcc AVcc+0.2 DAC12_0 IR=DAC12_1 IR =0 2.2V/3V DAC12_0 IR=1, DAC12_1 IR = 0 2.2V/3V Reference input p DAC12_0 IR=0, DAC12_1 IR = 1 2.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Conversion 1 Conversion 2 Conversion 3 VOUT 90% 90% 10% 10% tSRLH tSRHL Figure 26. Slew Rate Testing 12-bit DAC, dynamic specifications continued (TA = 25°C unless otherwise noted) PARAMETER BW−3dB TEST CONDITIONS 3 dB bandwidth, b d idth 3-dB VDC=1.5V, VAC=0.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) operational amplifier OA, supply specifications PARAMETER VCC ICC PSRR TEST CONDITIONS Supply voltage Supply current (see Note 1) Power supply rejection ratio VCC MIN — TYP MAX 2.2 UNIT 3.6 Fast Mode, Mode RRIP OFF 2 2 V/3 V 2.2 180 290 Medium Mode, Mode RRIP OFF 2 2 V/3 V 2.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) RO/P(OAx) Max RLoad ILoad AV CC OAx 2 CLoad O/P(OAx) Min 0.2V AV CC −0.2VAV V CC OUT Figure 29. OAx Output Resistance Tests operational amplifier OA, dynamic specifications PARAMETER SR TEST CONDITIONS Slew rate VCC TYP MAX UNIT — 1.2 Medium Mode — 0.8 Slow Mode — 0.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) Flash Memory TEST CONDITIONS PARAMETER VCC(PGM/ VCC MIN NOM MAX UNIT Program and Erase supply voltage 2.7 3.6 V fFTG Flash Timing Generator frequency 257 476 kHz IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA IERASE Supply current from DVCC during erase 2.7 V/ 3.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 APPLICATION INFORMATION input/output schematic Port P1, P1.0 to P1.5, input/output with Schmitt-trigger Pad Logic DVSS DVSS CAPD.x P1SEL.x 0: Input 1: Output 0 P1DIR.x Direction Control From Module 1 0 1 P1OUT.x Module X OUT Bus Keeper P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1IN.x EN Module X IN D P1IE.x P1IRQ.x P1IFG.x EN Interrupt Edge Select Q Set P1IES.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) Port P1, P1.6, P1.7, input/output with Schmitt-trigger Pad Logic Note: Port function is active if CAPD.6 = 0 CAPD.6 P1SEL.6 0: Input 1: Output 0 P1DIR.6 P1.6/ CA0 1 P1DIR.6 0 P1OUT.6 1 DVSS Bus Keeper P1IN.6 EN D unused P1IE.7 EN P1IRQ.07 Interrupt Edge Select Q P1IFG.7 Set P1IES.x P1SEL.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger Pad Logic DVSS DVSS P2SEL.x 0: Input 1: Output 0 P2DIR.x Direction Control From Module 1 0 1 P2OUT.x Module X OUT Bus Keeper P2.0/TA2 P2.4/UTXD0 P2IN.x P2.5/URXD0 EN D Module X IN P2IE.x P2IRQ.x P2IFG.x EN Interrupt Edge Select Q Set P2IES.x Note: P2SEL.x x {0,4,5} PnSel.x PnDIR.x Dir.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P2, P2.1 to P2.3, input/output with Schmitt-trigger Pad Logic DVSS DVSS Module IN of pin P1.3/TBOUTH/SVSOUT P1DIR.3 P1SEL.3 P2SEL.x 0: Input 1: Output 0 P2DIR.x Direction Control From Module P2OUT.x 1 0 1 Module X OUT Bus Keeper P2.1/TB0 P2.2/TB1 P2IN.x P2.3/TB2 EN D Module X IN P2IE.x P2IRQ.x Q P2IFG.x EN Interrupt Edge Select Set P2IES.x Note: P2SEL.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P2, P2.6 to P2.7, input/output with Schmitt-trigger 0: Port active 1: Segment xx function active Pad Logic Port/LCD‡ Segment xx‡ P2SEL.x 0: Input 1: Output 0 P2DIR.x Direction Control From Module 1 0 P2OUT.x 1 Module X OUT Bus Keeper P2.6/CAOUT/S19 P2.7/ADC12CLK/S18 P2IN.x EN Module X IN D P2IE.x P2IRQ.x P2IFG.x EN Q Set Interrupt Edge Select P2IES.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P3, P3.0 to P3.3, input/output with Schmitt-trigger MSP430x43xIPN (80-Pin) Only 0: Port active 1: Segment xx function active LCDM.5 LCDM.6 LCDM.7 Pad Logic Segment xx x43xIPZ and x44xIPZ have not segment Function on Port P3: Both lines are low. P3SEL.x 0: Input 1: Output 0 P3DIR.x Direction Control From Module 1 0 1 P3OUT.x Module X OUT Bus Keeper P3.0/STE0/S31 P3.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P3, P3.4 to P3.7, input/output with Schmitt-trigger 0: Port active 1: Segment xx function active Pad Logic LCDM.7 Segment xx P3SEL.x 0: Input 1: Output 0 P3DIR.x Direction Control From Module 1 0 P3OUT.x 1 Module X OUT Bus Keeper P3.4/S27 P3.5/S26 P3.6/S25/DMAE0 P3.7/S24 P3IN.x EN Module X IN D Note: 4
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P4, P4.0 to P4.5, input/output with Schmitt-trigger 0: Port active 1: Segment xx function active Pad Logic Port/LCD Segment xx P4SEL.x 0: Input 1: Output 0 P4DIR.x Direction Control From Module 1 0 1 P4OUT.x Module X OUT Bus Keeper P4.0/S9 P4.1/S8 P4.2/S7 P4.3/S6 P4.4/S5 P4.5/S4 P4IN.x EN Module X IN Note: D 0
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P4, P4.6, input/output with Schmitt-trigger INCH=15# a15 # 0: Segment S3 disabled 1: Segment S3 enabled Pad Logic 1, if LCDM > 020h Segment S3 P4SEL.6 0: input 1: output 0 P4DIR.6 Direction Control From Module 1 0 P4OUT.6 1 Module XOUT Bus keeper P4.6/S3/A15 P4IN.6 EN D Module X IN # Signal from or to ADC12 PnSEL.x P4SEL.6 DEVICE xG43xIPN 80-pin QFP PnDIR.x P4DIR.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P4, P4.7, input/output with Schmitt-trigger INCH=14# OAADC0 a14# 0: Segment S2 disabled 1: Segment S2 enabled Pad Logic 1, if LCDM > 020h Segment S2 P4SEL.7 0: input 1: output 0 P4DIR.7 Direction Control From Module 1 0 P4OUT.7 1 Module XOUT Bus keeper P4.7/S2/A14 P4IN.7 EN D Module X IN # Signal from or to ADC12 PnSel.x PnDIR.x P4Sel.7 P4DIR.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P5, P5.0, input/output with Schmitt-trigger OAADC0 INCH=13# a13 # 0: Segment S1 disabled 1: Segment S1 enabled Pad Logic 1, if LCDM > 020h Segment S1 P5SEL.0 0: input 1: output 0 P5DIR.0 Direction Control From Module 1 0 P5OUT.0 1 Module XOUT Bus keeper P5.0/S1/A13 P5IN.0 EN D Module X IN # Signal from or to ADC12 PnSEL.x P5SEL.0 DEVICE xG43xIPN 80-pin QFP PnDIR.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P5, P5.1, input/output with Schmitt-trigger OAADC0 INCH=12# a12# 0: Segment S0 disabled 1: Segment S0 enabled 1, if LCDM > 020h Pad Logic DAC12.1OPS Segment S0 P5SEL.1 0: input 1: output 0 P5DIR.1 Direction Control From Module 1 0 P5OUT.1 1 Module XOUT Bus keeper P5.1/S0/ A12/DAC1 P5IN.1 EN Module X IN D ’0’, if DAC12.1CALON=0 AND DAC12.1AMPx>1 AND DAC12.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P5, P5.1, input/output with Schmitt-trigger (continued) PnSEL.x PnDIR.x Dir. Control from Module PnOUT.x Module X OUT PnIN.x Module X IN Segment Port/LCD P5SEL.1 P5DIR.1 P5DIR.1 P5OUT.1 DVSS P5IN.1 Unused S0 0: LCDM<20h port P5, P5.2 to P5.4, input/output with Schmitt-trigger 0: Port active 1: LCD function active Port/LCD LCD signal Pad Logic P5SEL.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P5, P5.5 to P5.7, input/output with Schmitt-trigger 0: Port active 1: LCD function active Port/LCD LCD signal Pad Logic P5SEL.x 0: Input 1: Output 0 P5DIR.x Direction Control From Module 1 0 1 P5OUT.x Module X OUT Bus Keeper P5.5/R13 P5.6/R23 P5.7/R33 P5IN.x EN Module X IN D Note: 60 5
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger INCH=x ax †, # †, # P6SEL.x † † P6DIR.x Direction Control From Module † P6OUT.x 0 1 0 1 Module XOUT P6IN.x Pad Logic 0: input 1: output Bus keeper P6.0/A0/OA0I0 P6.2/A2/OA0I1 P6.4/A4/OA1I0 † EN † Module X IN D + − † x = {0, 2, 4} # OA0 / OA1 Signal from or to ADC12 PnSel.x PnDIR.x Dir.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P6, P6.1, input/output with Schmitt-trigger INCH=1# a1 # P6SEL.1 0 P6DIR.1 Direction Control From Module P6OUT.1 Pad Logic 0: input 1: output 1 0 1 Module XOUT Bus keeper P6.1/A1/OA0O P6IN.1 EN Module X IN D ’1’, if OAADC1 = 1 OR OAFCx = 0 0 + OA0 1 − # OA0 Signal from or to ADC12 PnSel.x PnDIR.x Dir. Control From Module PnOUT.x Module X OUT PnIN.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P6, P6.3, input/output with Schmitt-trigger INCH=3# a3 # P6SEL.3 0 P6DIR.3 Direction Control From Module P6OUT.3 Pad Logic 0: input 1: output 1 0 1 Module XOUT Bus keeper P6.3/A3/OA1I1/OA1O P6IN.3 EN Module X IN D ’1’, if OAADC1 = 1 OR OAFCx = 0 0 + OA1 1 − # OA1 Signal from or to ADC12 PnSel.x PnDIR.x Dir. Control From Module PnOUT.x Module X OUT PnIN.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P6, P6.5, input/output with Schmitt-trigger INCH=5# a5 # P6SEL.5 0 P6DIR.5 Direction Control From Module P6OUT.5 Pad Logic 0: input 1: output 1 0 1 Module XOUT Bus keeper P6.5/A5/OA2I1/OA2O P6IN.5 EN Module X IN D ’1’, if OAADC1 = 1 OR OAFCx = 0 0 + OA2 1 − # OA2 Signal from or to ADC12 PnSel.x PnDIR.x Dir. Control From Module PnOUT.x Module X OUT PnIN.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P6, P6.6, input/output with Schmitt-trigger 0: Port active, T−Switch off 1: T−Switch is on, Port disabled INCH=6# a6 # ’1’, if DAC12.0AMP>0 DAC12.0OPS P6SEL.6 P6DIR.6 0 P6DIR.6 1 0: input 1: output Pad Logic 0 P6OUT.6 1 DVSS Bus keeper P6.6/A6/DAC0/OA2I0 P6IN.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) port P6, P6.7, input/output with Schmitt-trigger To SVS Mux (15) $ 0: Port active, T−Switch off 1: T−Switch is on, Port disabled INCH=7# a7 # ’1’, if DAC12.1AMP>0 DAC12.1OPS ’1’, if VLD=15 * P6SEL.7 P6DIR.7 0: input 1: output 0 Pad Logic 1 P6DIR.7 0 P6OUT.7 1 DVSS Bus keeper P6.7/A7/ DAC1/SVSIN P6IN.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) VeREF+/DAC0 DAC12.0OPS 0 DAC0_2_OA P6.6/A6/DAC0/OA2I0 1 Reference Voltage to DAC1 Reference Voltage to ADC12 Reference Voltage to DAC0 # Ve REF+ /DAC0 ’0’, if DAC12CALON = 0 DAC12AMPx>1 AND DAC12OPS=1 + − 1 0 ’1’, if DAC12AMPx>1 ’1’, if DAC12AMPx=1 DAC12OPS # If the reference of DAC0 is taken from pin VeREF+ /DAC0, unpredictable voltage levels will be on pin.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 input/output schematic (continued) JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output TDO Controlled by JTAG Controlled by JTAG TDO/TDI JTAG Controlled by JTAG DVCC TDI Burn and Test Fuse TDI/TCLK Test and Emulation DVCC TMS Module TMS DVCC TCK TCK RST/NMI Tau ~ 50 ns Brownout TCK 68 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • G
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
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MSP430FG43x MIXED SIGNAL MICROCONTROLLER SLAS380C − APRIL 2004 − REVISED MARCH 2011 Data Sheet Revision History Literature Number Summary SLAS380B Updated functional block diagram (page 3) Corrected I/O column for VeREF+/DAC0 in MSP430FG43x Terminal Functions table; changed from I to I/O (page 4) Clarified test conditions in recommended operating conditions table (page 20) Clarified test conditions in electrical characteristics table (page 21) Corrected y-axis unit on Figures 6 and 7; changed from V to
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430FG437IPNR LQFP PN 80 1000 330.0 24.4 14.6 14.6 1.9 20.0 24.0 Q2 MSP430FG438IPNR LQFP PN 80 1000 330.0 24.4 14.6 14.6 1.9 20.0 24.0 Q2 MSP430FG439IPNR LQFP PN 80 1000 330.0 24.4 14.6 14.6 1.9 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430FG437IPNR LQFP PN 80 1000 367.0 367.0 45.0 MSP430FG438IPNR LQFP PN 80 1000 367.0 367.0 45.0 MSP430FG439IPNR LQFP PN 80 1000 367.0 367.0 45.
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MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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