Datasheet
Table Of Contents
- features
- description
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC1/2 excluding external current
- SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx, TBx
- leakage current − Ports P1, P2, P3, P4, P5, and P6
- outputs − Ports P1, P2, P3, P4, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- Flash Memory
- JTAG Interface
- JTAG Fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
- Port P1, P1.6, P1.7, input/output with Schmitt-trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
- port P2, P2.1 to P2.3, input/output with Schmitt-trigger
- port P2, P2.6 to P2.7, input/output with Schmitt-trigger
- port P3, P3.0 to P3.3, input/output with Schmitt-trigger
- port P3, P3.4 to P3.7, input/output with Schmitt-trigger
- port P4, P4.0 to P4.5, input/output with Schmitt-trigger
- port P4, P4.6, input/output with Schmitt-trigger
- port P4, P4.7, input/output with Schmitt-trigger
- port P5, P5.0, input/output with Schmitt-trigger
- port P5, P5.1, input/output with Schmitt-trigger
- port P5, P5.2 to P5.4, input/output with Schmitt-trigger
- port P5, P5.5 to P5.7, input/output with Schmitt-trigger
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger
- port P6, P6.1, input/output with Schmitt-trigger
- port P6, P6.3, input/output with Schmitt-trigger
- port P6, P6.5, input/output with Schmitt-trigger
- port P6, P6.6, input/output with Schmitt-trigger
- port P6, P6.7, input/output with Schmitt-trigger
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History
- Corrections to MSP430FG43x Data Sheet (SLAS380C)
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380C − APRIL 2004 − REVISED MARCH 2011
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
Timer_B3 TBCCR0 CCIFG0 (see Note 2) Maskable 0FFFAh 13
Timer_B3
TBCCR1 CCIFG1, TBCCR2 CCIFG2,
TBIFG (see Notes 1 and 2)
Maskable 0FFF8h 12
Comparator_A CAIFG Maskable 0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USART0 Receive URXIFG0 Maskable 0FFF2h 9
USART0 Transmit UTXIFG0 Maskable 0FFF0h 8
ADC12 ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 7
Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0FFECh 6
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable 0FFEAh 5
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 4
DAC12
DMA
DAC12.0IFG, DAC12.1IFG,
DMA0IFG (see Notes 1 and 2)
Maskable 0FFE6h 3
0FFE4h 2
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot
disable it.