Datasheet
Table Of Contents
- features
- description
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC1/2 excluding external current
- SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx, TBx
- leakage current − Ports P1, P2, P3, P4, P5, and P6
- outputs − Ports P1, P2, P3, P4, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- Flash Memory
- JTAG Interface
- JTAG Fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
- Port P1, P1.6, P1.7, input/output with Schmitt-trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
- port P2, P2.1 to P2.3, input/output with Schmitt-trigger
- port P2, P2.6 to P2.7, input/output with Schmitt-trigger
- port P3, P3.0 to P3.3, input/output with Schmitt-trigger
- port P3, P3.4 to P3.7, input/output with Schmitt-trigger
- port P4, P4.0 to P4.5, input/output with Schmitt-trigger
- port P4, P4.6, input/output with Schmitt-trigger
- port P4, P4.7, input/output with Schmitt-trigger
- port P5, P5.0, input/output with Schmitt-trigger
- port P5, P5.1, input/output with Schmitt-trigger
- port P5, P5.2 to P5.4, input/output with Schmitt-trigger
- port P5, P5.5 to P5.7, input/output with Schmitt-trigger
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger
- port P6, P6.1, input/output with Schmitt-trigger
- port P6, P6.3, input/output with Schmitt-trigger
- port P6, P6.5, input/output with Schmitt-trigger
- port P6, P6.6, input/output with Schmitt-trigger
- port P6, P6.7, input/output with Schmitt-trigger
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History
- Corrections to MSP430FG43x Data Sheet (SLAS380C)
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380C − APRIL 2004 − REVISED MARCH 2011
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
MSP430FG43x Terminal Functions (Continued)
TERMINAL
PN
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
P3.3/UCLK0/S28 40 I/O
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI mode, clock o/p—USART0/SPI mode
/ LCD segment output 28
P3.2/SOMI0/S29 41 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 29
P3.1/SIMO0/S30 42 I/O General-purpose digital I/O / slave out/master out of USART0/SPI mode / LCD segment output 30
P3.0/STE0/S31 43 I/O General-purpose digital I/O / slave transmit enable-USART0/SPI mode / LCD segment output 31
COM0 44 O Common output, COM0−3 are used for LCD backplanes.
P5.2/COM1 45 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2 46 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3 47 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
R03 48 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 49 I/O General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3)
P5.6/R23 50 I/O General-purpose digital I/O / input port of second most positive analog LCD level (V2)
P5.7/R33 51 I/O General-purpose digital I/O / output port of most positive analog LCD level (V1)
DV
CC2
52 Digital supply voltage, positive terminal.
DV
SS2
53 Digital supply voltage, negative terminal.
P2.5/URXD0 54 I/O General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0 55 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 56 I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 57 I/O
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 58 I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 59 I/O
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA13 60 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 61 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
62 I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK
63 I/O General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
64 I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B3 TB0 to TB2
/ SVS: output of SVS comparator
P1.2/TA1 65 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output
P1.1/TA0/MCLK 66 I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this
pin / BSL receive
P1.0/TA0 67 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT 68 O Output terminal of crystal oscillator XT2
XT2IN 69 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 70 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 71 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 72 I Test mode select. TMS is used as an input port for device programming and test.
TCK 73 I Test clock. TCK is the clock input port for device programming and test.