Datasheet
Table Of Contents
- features
- description
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC1/2 excluding external current
- SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx, TBx
- leakage current − Ports P1, P2, P3, P4, P5, and P6
- outputs − Ports P1, P2, P3, P4, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- Flash Memory
- JTAG Interface
- JTAG Fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
- Port P1, P1.6, P1.7, input/output with Schmitt-trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
- port P2, P2.1 to P2.3, input/output with Schmitt-trigger
- port P2, P2.6 to P2.7, input/output with Schmitt-trigger
- port P3, P3.0 to P3.3, input/output with Schmitt-trigger
- port P3, P3.4 to P3.7, input/output with Schmitt-trigger
- port P4, P4.0 to P4.5, input/output with Schmitt-trigger
- port P4, P4.6, input/output with Schmitt-trigger
- port P4, P4.7, input/output with Schmitt-trigger
- port P5, P5.0, input/output with Schmitt-trigger
- port P5, P5.1, input/output with Schmitt-trigger
- port P5, P5.2 to P5.4, input/output with Schmitt-trigger
- port P5, P5.5 to P5.7, input/output with Schmitt-trigger
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger
- port P6, P6.1, input/output with Schmitt-trigger
- port P6, P6.3, input/output with Schmitt-trigger
- port P6, P6.5, input/output with Schmitt-trigger
- port P6, P6.6, input/output with Schmitt-trigger
- port P6, P6.7, input/output with Schmitt-trigger
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History
- Corrections to MSP430FG43x Data Sheet (SLAS380C)

MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380C − APRIL 2004 − REVISED MARCH 2011
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 21)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Resolution (12-bit Monotonic) 12 bits
INL
Integral nonlinearity
V
ref
= 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
±20
±80
LSB
INL
Integral
nonlinearity
(see Note 1)
V
ref
= 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
±2.0 ±8.0 LSB
DNL
Differential nonlinearity
V
ref
= 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
±04
±10
LSB
DNL
Differential
nonlinearity
(see Note 1)
V
ref
= 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
±0.4 ±1.0 LSB
Offset voltage w/o
calibration
V
ref
= 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
±21
E
O
calibration
(see Notes 1, 2)
V
ref
= 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
±21
mV
Offset voltage with
calibration
V
ref
= 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
±25
mV
calibration
(see Notes 1, 2)
V
ref
= 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
±2.5
d
E(O)
/d
T
Offset error
temperature coefficient
(see Note 1)
2.2V/3V ±30 μV/C
E
Gain error (see Note 1)
V
REF
= 1.5 V 2.2V
±350
% FSR
E
G
Gain error (see Note 1)
V
REF
= 2.5 V 3V
±3.50 % FSR
d
E(G)
/d
T
Gain temperature
coefficient (see Note 1)
2.2V/3V 10
ppm of
FSR/°C
Time for offset calibration
DAC12AMPx=2 2.2V/3V 100
t
Offset_Cal
Time for offset calibration
(see Note 3)
DAC12AMPx=3,5 2.2V/3V 32
ms
t
Offset
_
Cal
(see Note 3)
DAC12AMPx=4,6,7 2.2V/3V 6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. V
DAC12_xOUT
= E
O
+ (1 + E
G
) * (V
eREF+
/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
Positive
Negative
V
R+
Gain Error
Offset Error
DAC Code
DAC V
OUT
Ideal transfer
function
R
Load
=
AV
CC
C
Load
= 100pF
2
DAC Output
Figure 21. Linearity Test Load Conditions and Gain/Offset Definition