Datasheet
Table Of Contents
- features
- description
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC1/2 excluding external current
- SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx, TBx
- leakage current − Ports P1, P2, P3, P4, P5, and P6
- outputs − Ports P1, P2, P3, P4, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- Flash Memory
- JTAG Interface
- JTAG Fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
- Port P1, P1.6, P1.7, input/output with Schmitt-trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
- port P2, P2.1 to P2.3, input/output with Schmitt-trigger
- port P2, P2.6 to P2.7, input/output with Schmitt-trigger
- port P3, P3.0 to P3.3, input/output with Schmitt-trigger
- port P3, P3.4 to P3.7, input/output with Schmitt-trigger
- port P4, P4.0 to P4.5, input/output with Schmitt-trigger
- port P4, P4.6, input/output with Schmitt-trigger
- port P4, P4.7, input/output with Schmitt-trigger
- port P5, P5.0, input/output with Schmitt-trigger
- port P5, P5.1, input/output with Schmitt-trigger
- port P5, P5.2 to P5.4, input/output with Schmitt-trigger
- port P5, P5.5 to P5.7, input/output with Schmitt-trigger
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger
- port P6, P6.1, input/output with Schmitt-trigger
- port P6, P6.3, input/output with Schmitt-trigger
- port P6, P6.5, input/output with Schmitt-trigger
- port P6, P6.6, input/output with Schmitt-trigger
- port P6, P6.7, input/output with Schmitt-trigger
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History
- Corrections to MSP430FG43x Data Sheet (SLAS380C)

MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380C − APRIL 2004 − REVISED MARCH 2011
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
f
ADC12CLK
For specified performance of
ADC12 linearity parameters
V
CC
=
2.2V/3 V
0.45 5 6.3 MHz
f
ADC12OSC
Internal ADC12
oscillator
ADC12DIV=0,
f
ADC12CLK
=f
ADC12OSC
V
CC
=
2.2 V/ 3 V
3.7 5 6.3 MHz
t
Conversion time
C
VREF+
≥ 5 μF, Internal oscillator,
f
ADC12OSC
= 3.7 MHz to 6.3 MHz
V
CC
=
2.2 V/ 3 V
2.06 3.51 μs
t
CONVERT
Conversion time
External f
ADC12CLK
from ACLK, MCLK or SMCLK:
ADC12SSEL ≠ 0
13×ADC12DIV×
1/f
ADC12CLK
μs
t
ADC12ON
Turn on settling time of
the ADC
(see Note 1) 100 ns
R
S
= 400 Ω, R
I
= 1000 Ω,
V
CC
= 3 V 1220
t
Sample
Sampling time
R
S
=
400
Ω
,
R
I
=
1000
Ω
,
C
I
= 30 pF, τ = [R
S
+ R
I
] x C
I
(see Note 2)
V
CC
=
2.2 V
1400
ns
NOTES: 1. The condition is that the error in a conversion started after t
ADC12ON
is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
t
Sample
= ln(2
n+1
) x (R
S
+ R
I
) x C
I
+ 800 ns where n = ADC resolution = 12, R
S
= external source resistance.
12-bit ADC, linearity parameters
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
E
Integral linearity error
1.4 V ≤ (V
eREF+
− V
REF−
/V
eREF−
) min ≤ 1.6 V
V
CC
=
±2
LSB
E
I
Integral linearity error
1.6 V < (V
eREF+
− V
REF−
/V
eREF−
) min ≤ [V
AVCC
]
V
CC
=
2.2 V/3 V
±1.7
LSB
E
D
Differential linearity
error
(V
eREF+
− V
REF−
/V
eREF−
)
min
≤ (V
eREF+
− V
REF−
/V
eREF−
),
C
VREF+
= 10 μF (tantalum) and 100 nF (ceramic)
V
CC
=
2.2 V/3 V
±1 LSB
E
O
Offset error
(V
eREF+
− V
REF−
/V
eREF−
)
min
≤ (V
eREF+
− V
REF−
/V
eREF−
),
Internal impedance of source R
S
< 100 Ω,
C
VREF+
= 10 μF (tantalum) and 100 nF (ceramic)
V
CC
=
2.2 V/3 V
±2 ±4 LSB
E
G
Gain error
(V
eREF+
− V
REF−
/V
eREF−
)
min
≤ (V
eREF+
− V
REF−
/V
eREF−
),
C
VREF+
= 10 μF (tantalum) and 100 nF (ceramic)
V
CC
=
2.2 V/3 V
±1.1 ±2 LSB
E
T
Total unadjusted
error
(V
eREF+
− V
REF−
/V
eREF−
)
min
≤ (V
eREF+
− V
REF−
/V
eREF−
),
C
VREF+
= 10 μF (tantalum) and 100 nF (ceramic)
V
CC
=
2.2 V/3 V
±2 ±5 LSB