Datasheet
Table Of Contents
- features
- description
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC1/2 excluding external current
- SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx, TBx
- leakage current − Ports P1, P2, P3, P4, P5, and P6
- outputs − Ports P1, P2, P3, P4, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- Flash Memory
- JTAG Interface
- JTAG Fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
- Port P1, P1.6, P1.7, input/output with Schmitt-trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
- port P2, P2.1 to P2.3, input/output with Schmitt-trigger
- port P2, P2.6 to P2.7, input/output with Schmitt-trigger
- port P3, P3.0 to P3.3, input/output with Schmitt-trigger
- port P3, P3.4 to P3.7, input/output with Schmitt-trigger
- port P4, P4.0 to P4.5, input/output with Schmitt-trigger
- port P4, P4.6, input/output with Schmitt-trigger
- port P4, P4.7, input/output with Schmitt-trigger
- port P5, P5.0, input/output with Schmitt-trigger
- port P5, P5.1, input/output with Schmitt-trigger
- port P5, P5.2 to P5.4, input/output with Schmitt-trigger
- port P5, P5.5 to P5.7, input/output with Schmitt-trigger
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger
- port P6, P6.1, input/output with Schmitt-trigger
- port P6, P6.3, input/output with Schmitt-trigger
- port P6, P6.5, input/output with Schmitt-trigger
- port P6, P6.6, input/output with Schmitt-trigger
- port P6, P6.7, input/output with Schmitt-trigger
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History
- Corrections to MSP430FG43x Data Sheet (SLAS380C)

MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380C − APRIL 2004 − REVISED MARCH 2011
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
typical characteristics
V
CC
0
0.5
1
1.5
2
t
pw
t
pw
− Pulse Width − μs
3 V
0.001 1 1000
t
f
t
r
t
pw
− Pulse Width − μs
t
f
= t
r
Typical Conditions
V
CC
= 3 V
V
CC(drop)
− V
V
CC(drop)
Figure 12. V
CC(drop)
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dV
CC
/dt > 30 V/ms (see Figure 13) 5 150 μs
t
(SVSR)
dV
CC
/dt ≤ 30 V/ms 2000 μs
t
d(SVSon)
SVSon, switch from VLD=0 to VLD ≠ 0, V
CC
= 3 V 150 300 μs
t
settle
VLD ≠ 0
‡
12 μs
V
(SVSstart)
VLD ≠ 0, V
CC
/dt ≤ 3 V/s (see Figure 13) 1.55 1.7 V
VLD = 1 70 120 155 mV
V
h
y
s
(
SVS_IT−
)
V
CC
/dt ≤ 3 V/s (see Figure 13)
VLD = 2 .. 14
V
(SVS_IT−)
x 0.001
V
(SVS_IT−)
x 0.016
V
hys(SVS
_
IT
−
)
V
CC
/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7
VLD = 15 4.4 20 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.23
VLD = 3 2.05 2.2 2.35
VLD = 4 2.14 2.3 2.46
VLD = 5 2.24 2.4 2.58
VLD = 6 2.33 2.5 2.69
V /dt ≤ 3 V/s (see Figure 13)
VLD = 7 2.46 2.65 2.84
V
(SVS IT )
V
CC
/dt ≤ 3 V/s (see Figure 13)
VLD = 8 2.58 2.8 2.97
V
V
(SVS_IT−)
VLD = 9 2.69 2.9 3.10
V
VLD = 10 2.83 3.05 3.26
VLD = 11 2.94 3.2 3.39
VLD = 12 3.11 3.35 3.58
†
VLD = 13 3.24 3.5 3.73
†
VLD = 14 3.43 3.7
†
3.96
†
V
CC
/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7
VLD = 15 1.1 1.2 1.3
I
CC(SVS)
(see Note 1)
VLD ≠ 0, V
CC
= 2.2 V/3 V 10 15 μA
†
The recommended operating voltage range is limited to 3.6 V.
‡
t
settle
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the I
CC
current consumption data.