Datasheet
Table Of Contents
- features
- description
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC1/2 excluding external current
- SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx, TBx
- leakage current − Ports P1, P2, P3, P4, P5, and P6
- outputs − Ports P1, P2, P3, P4, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- Flash Memory
- JTAG Interface
- JTAG Fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
- Port P1, P1.6, P1.7, input/output with Schmitt-trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
- port P2, P2.1 to P2.3, input/output with Schmitt-trigger
- port P2, P2.6 to P2.7, input/output with Schmitt-trigger
- port P3, P3.0 to P3.3, input/output with Schmitt-trigger
- port P3, P3.4 to P3.7, input/output with Schmitt-trigger
- port P4, P4.0 to P4.5, input/output with Schmitt-trigger
- port P4, P4.6, input/output with Schmitt-trigger
- port P4, P4.7, input/output with Schmitt-trigger
- port P5, P5.0, input/output with Schmitt-trigger
- port P5, P5.1, input/output with Schmitt-trigger
- port P5, P5.2 to P5.4, input/output with Schmitt-trigger
- port P5, P5.5 to P5.7, input/output with Schmitt-trigger
- port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger
- port P6, P6.1, input/output with Schmitt-trigger
- port P6, P6.3, input/output with Schmitt-trigger
- port P6, P6.5, input/output with Schmitt-trigger
- port P6, P6.6, input/output with Schmitt-trigger
- port P6, P6.7, input/output with Schmitt-trigger
- VeREF+/DAC0
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History
- Corrections to MSP430FG43x Data Sheet (SLAS380C)

MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380C − APRIL 2004 − REVISED MARCH 2011
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
OA
The MSP430FG43x has three configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offers a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
USART0
The MSP430FG43x has one hardware universal synchronous/asynchronous receive transmit (USART)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4
pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Device Input Module Input Module Module Output
Output Pin Number
PN
Device
Input
Signal
Module
Input
Name
Module
Block
Module
Output
Signal
PN
62 - P1.5 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK
Timer NA
62 - P1.5 TACLK INCLK
67 - P1.0 TA0 CCI0A
67 - P1.0
66 - P1.1 TA0 CCI0B
CCR0
TA0
DV
SS
GND
CCR0 TA0
DV
CC
V
CC
65 - P1.2 TA1 CCI1A
65 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1
ADC12 (internal)
DV
SS
GND
CCR1 TA1
DV
CC
V
CC
59 - P2.0 TA2 CCI2A
59 - P2.0
ACLK (internal) CCI2B
CCR2
TA2
DV
SS
GND
CCR2 TA2
DV
CC
V
CC