Datasheet
Table Of Contents
- features
- description
- Available Options
- pin designation, DL package
- pin designation, RGZ package
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx
- leakage current − Ports P1, P2, P5, and P6
- outputs − Ports P1, P2, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- POR/brownout reset (BOR)
- DCO
- crystal oscillator, LFXT1 oscillator
- SD16_A, power supply and recommended operating conditions
- SD16_A, input range
- SD16_A, performance
- SD16_A, temperature sensor
- SD16_A, built-in voltage reference
- SD16_A, reference output buffer
- SD16_A, external reference input
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- switches to ground
- flash memory
- JTAG interface
- JTAG fuse
- input/output schematics
- Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt−trigger
- Port P1 pin schematic: P1.2, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.4, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.6, input/output with Schmitt−trigger and analog functions
- Port P2 pin schematic: P2.0 to P2.1, input/output with Schmitt−trigger, LCD and analog functions
- Port P2 pin schematic: P2.2 to P2.7, input/output with Schmitt−trigger, LCD and analog functions
- Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt−trigger and LCDfunctions
- Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt−trigger and LCD functions
- Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt−trigger and analog functions
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- Data Sheet Revision History
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME DL
NO.
RGZ
NO.
I/O
DESCRIPTION
TDO/TDI 1 43 I/O Test data output. TDO/TDI data output or programming data input terminal
TDI/TCLK 2 44 I Test data input / test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 3 45 I Test mode select. TMS is used as an input port for device programming and test.
TCK 4 46 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 5 47 I General-purpose digital I/O / reset input / nonmaskable interrupt input
DV
CC
6 48 Digital supply voltage, positive terminal
DV
SS
7 1 Digital supply voltage, negative terminal
XIN 8 2 I Input terminal of crystal oscillator XT1
XOUT 9 3 O Output terminal of crystal oscillator XT1
AV
SS
10 4 Analog supply voltage, negative terminal
AV
CC
11 5 Analog supply voltage, positive terminal
V
REF
12 6 I/O Analog reference voltage
P6.0/A0+/OA0O 13 7 I/O General-purpose digital I/O / analog input A0+ / OA0 output
P6.1/A0−/OA0FB 14 8 I/O General-purpose digital I/O / analog input A0− / OA0 feedback input
P6.2/A1+/OA1O 15 9 I/O General-purpose digital I/O / analog input A1+ / OA1 output
P6.3/A1−/OA1FB 16 10 I/O General-purpose digital I/O / analog input A1− / OA1 feedback input
P6.4/OA0I1 17 11 I/O General-purpose digital I/O / OA0 input multiplexer on −terminal
P6.5/OA0I2 18 12 I/O General-purpose digital I/O / OA0 input multiplexer on −terminal
P6.6/OA1I1 19 13 I/O General-purpose digital I/O / OA1 input multiplexer on −terminal
P6.7/OA1I2 20 14 I/O General-purpose digital I/O / OA1 input multiplexer on −terminal
P1.7/A2+ 21 15 I/O General-purpose digital I/O / analog input A2+
P1.6/A2−/OA0I0 22 16 I/O General-purpose digital I/O / analog input A2− / OA0 input multiplexer on +terminal
P1.5/TACLK/ACLK/A3+ 23 17 I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8) / analog input A3+
P1.4/A3−/OA1I0/DAC0 24 18 I/O
General-purpose digital I/O / analog input A3− /
OA1 input multiplexer on +terminal / DAC12 output
P1.3/TA2/A4+ 25 19 I/O
General-purpose digital I/O / Timer_A, Capture: CCI2A, compare: Out2 output /
analog input A4+
P1.2/TA1/A4− 26 20 I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output /
analog input A4−
P1.1/TA0/MCLK 27 21 I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an
input on this pin / BSL Receive
P1.0/TA0 28 22 I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL
transmit
LCDREF/R13 29 23 External LCD reference voltage input / input port of third most positive analog LCD level (V4
or V3)
LCDCAP/R23 30 24 Capacitor connection for LCD charge pump /
input port of second most positive analog LCD level (V2)
P5.1/S0 31 25 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 32 26 I/O General-purpose digital I/O / LCD segment output 1
P5.5/S2 33 27 I/O General-purpose digital I/O / LCD segment output 2
P5.6/S3 34 28 I/O General-purpose digital I/O / LCD segment output 3
P5.7/S4 35 29 I/O General-purpose digital I/O / LCD segment output 4
S5 36 30 O LCD segment output 5
P2.7/S6 37 31 I/O General-purpose digital I/O / LCD segment output 6
P2.6/S7 38 32 I/O General-purpose digital I/O / LCD segment output 7