Datasheet
Table Of Contents
- features
- description
- Available Options
- pin designation, DL package
- pin designation, RGZ package
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx
- leakage current − Ports P1, P2, P5, and P6
- outputs − Ports P1, P2, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- POR/brownout reset (BOR)
- DCO
- crystal oscillator, LFXT1 oscillator
- SD16_A, power supply and recommended operating conditions
- SD16_A, input range
- SD16_A, performance
- SD16_A, temperature sensor
- SD16_A, built-in voltage reference
- SD16_A, reference output buffer
- SD16_A, external reference input
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- switches to ground
- flash memory
- JTAG interface
- JTAG fuse
- input/output schematics
- Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt−trigger
- Port P1 pin schematic: P1.2, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.4, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.6, input/output with Schmitt−trigger and analog functions
- Port P2 pin schematic: P2.0 to P2.1, input/output with Schmitt−trigger, LCD and analog functions
- Port P2 pin schematic: P2.2 to P2.7, input/output with Schmitt−trigger, LCD and analog functions
- Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt−trigger and LCDfunctions
- Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt−trigger and LCD functions
- Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt−trigger and analog functions
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- Data Sheet Revision History

MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
operational amplifier OA, dynamic specifications
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Fast Mode 1.2
SR Slew rate
Medium Mode
—
0.8
V/μs
SR
Slew
rate
Slow Mode 0.3
V/μs
Open-loop voltage gain — 100 dB
φ
m
Phase margin C
L
= 50 pF — 60 deg
Gain margin C
L
= 50 pF — 20 dB
Noninverting Fast Mode R 47kΩ C 50pF
22
Gain
-
bandwidth product
Noninverting, Fast Mode, R
L
= 47kΩ, C
L
= 50pF 2.2
GBW
Gain
-
bandwidth
product
(see Figure 19
Noninverting Medium Mode R 300kΩ C 50pF
2 2 V/3 V
14
MHz
GBW
(see Figure 19
Noninverting, Medium Mode, R
L
=300kΩ, C
L
= 50pF 2.2 V/3 V 1.4 MHz
GBW
(see
Figure
19
a
n
d
Fi
gu
r
e
2
0)
Noninverting Slow Mode R 300kΩ C 50pF
2.2
V/3
V
05
MHz
and
Figure
20)
Noninverting, Slow Mode, R
L
=300kΩ, C
L
= 50pF 0.5
t
en(on)
Enable time on t
on
, noninverting, Gain = 1 2.2 V/3 V 10 20 μs
t
en(off)
Enable time off 2.2 V/3 V 1 μs
Figure 19
Input Frequency − kHz
−80
−60
−40
−20
0
20
40
60
80
100
120
140
TYPICAL OPEN-LOOP GAIN vs FREQUENCY
Slow Mode
Fast Mode
Gain − dB
Medium Mode
0.001 0.01 0.1 1 10 100 1000 10000
Figure 20
Input Frequency − kHz
−250
−200
−150
−100
−50
0
TYPICAL PHASE vs FREQUENCY
Phase − degrees
Slow Mode
Fast Mode
Medium Mode
0.001 0.01 0.1 1 10 100 1000 10000
switches to ground
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
V
CC
Supply voltage 2.5 3.6 V
I
Input leaka
g
e current
T
A
= −40_C to + 55_C ±1 ±10
nA
I
lkg
Input
leakage
current
(see Note 1)
T
A
= 55_C to 85_C ±50
nA
I
IN
Input current Input switched to Ground. 0 100 μA
R
ON
On resistance I
IN
=100 μA, T
A
=−40°C to 85°C 10 Ω
NOTES: 1. ESD damage can degrade input current leakage.