Datasheet
Table Of Contents
- features
- description
- Available Options
- pin designation, DL package
- pin designation, RGZ package
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx
- leakage current − Ports P1, P2, P5, and P6
- outputs − Ports P1, P2, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- POR/brownout reset (BOR)
- DCO
- crystal oscillator, LFXT1 oscillator
- SD16_A, power supply and recommended operating conditions
- SD16_A, input range
- SD16_A, performance
- SD16_A, temperature sensor
- SD16_A, built-in voltage reference
- SD16_A, reference output buffer
- SD16_A, external reference input
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- switches to ground
- flash memory
- JTAG interface
- JTAG fuse
- input/output schematics
- Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt−trigger
- Port P1 pin schematic: P1.2, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.4, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.6, input/output with Schmitt−trigger and analog functions
- Port P2 pin schematic: P2.0 to P2.1, input/output with Schmitt−trigger, LCD and analog functions
- Port P2 pin schematic: P2.2 to P2.7, input/output with Schmitt−trigger, LCD and analog functions
- Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt−trigger and LCDfunctions
- Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt−trigger and LCD functions
- Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt−trigger and analog functions
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- Data Sheet Revision History

MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
operational amplifier OA, supply specifications
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
V
CC
Supply voltage — 2.2 3.6 V
Fast Mode
180
290
Sl t
Fast Mode 180 290
I
Su
pp
l
y
current
Medium Mode
2 2 V/3 V
110
190
A
I
CC
Supply
current
(see Note 1)
Medium Mode 2.2 V/3 V 110 190 μA
I
CC
(
see
N
o
t
e
1)
Slow Mode
2.2
V/3
V
50 80
μA
PSRR Power supply rejection ratio Non-inverting 2.2 V/3 V 70 dB
NOTES: 1. P6SEL.x = 1 or SD16AE.x = 1 for each corresponding pin when used in OA input or OA output mode.
operational amplifier OA, input/output specifications
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
V
I/P
Input voltage, I/P — −0.1 V
CC
−1.2 V
I
Input leaka
g
e current, I/P
T
A
= −40_C to 55_C −5 ±0.5 5 nA
I
Ikg
Input
leakage
current
,
I/P
(see Notes 1 and 2)
T
A
= 55_C to 85_C
—
−20 ±5 20 nA
Fast Mode 50
Medium Mode
f
V
(
I/P
)
= 1 kHz
80
V
Voltage noise density I/P
Slow Mode
f
V(I/P)
1
kHz
140
nV/√Hz
V
n
Voltage noise density, I/P
Fast Mode
—
30
nV/√Hz
Medium Mode
f
V
(
I/P
)
= 10 kHz
50
Slow Mode
f
V(I/P)
10
kHz
65
V
Offset voltage I/P
2 2 V/3 V
±10
mV
V
IO
Offset voltage, I/P 2.2 V/3 V ±10 mV
Offset temperature drift, I/P see Note 3 2.2 V/3 V ±10 μV/°C
Offset voltage drift
with supply, I/P
0.3V ≤ V
IN
≤ V
CC
−0.3 V
ΔV
CC
≤ ± 10%, T
A
= 25°C
2.2 V/3 V ±1.5 mV/V
V
High level output voltage O/P
Fast Mode, I
SOURCE
≤ −500 μA 2.2 V V
CC
−0.2 V
CC
V
V
OH
High-level output voltage, O/P
Slow Mode,I
SOURCE
≤ −150 μA 3 V V
CC
−0.1 V
CC
V
V
Low level output voltage O/P
Fast Mode, I
SOURCE
≤ +500 μA 2.2 V V
SS
0.2
V
V
OL
Low-level output voltage, O/P
Slow Mode,I
SOURCE
≤ +150 μA 3 V V
SS
0.1
V
CMRR Common-mode rejection ratio Non-inverting 2.2 V/3 V 70 dB
NOTES: 1. ESD damage can degrade input current leakage.
2. The input bias current is overridden by the input leakage current.
3. Characterized and calculated using the box method, not production tested.