Datasheet

PZ PACKAGE
1SD0P0
2SD0N0
3SD1P0
4SD1N0
5SD2P0
6SD2N0
7VREF
8AVSS
9AVCC
10VASYS
11P9.1/A5
12P9.2/A4
13P9.3/A3
14P1.0/PM_TA0.0/VeREF-/A2
15P1.1/PM_TA0.1/VeREF+/A1
16P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
17P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
18AUXVCC2
19AUXVCC1
20VDSYS
21DVCC
22DVSS
23VCORE
24XIN
25XOUT
26
AUXVCC3
27
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
28
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
29
LCDCAP/R33
30
P8.4/TA1.0
31
P8.5/TA1.1
32
COM0
33
COM1
34
COM2
35
COM3
36
P1.6/PM_UCA0CLK/COM4
37
P1.7/PM_UCB0CLK/COM5
38
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
39
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
40
P8.6/TA2.0
41
P8.7/TA2.1
42
P9.0/TACLK/RTCCLK
43
P2.2/PM_UCA2RXD/PM_UCA2SOMI
44
P2.3/PM_UCA2TXD/PM_UCA2SIMO
45
P2.4/PM_UCA1CLK
46
P2.5/PM_UCA2CLK
47
P2.6/PM_TA1.0
48
P2.7/PM_TA1.1
49
P3.0/PM_TA2.0/BSL_TX
50
P3.1/PM_TA2.1/BSL_RX
51 P3.2/PM_TACLK/PM_RTCCLK
52 P3.3/PM_TA0.2
53 P3.4/PM_SDCLK/S39
54 P3.5/PM_SD0DIO/S38
55 P3.6/PM_SD1DIO/S37
56 P3.7/PM_SD2DIO/S36
57 P4.0/S35
58 P4.1/S34
59 P4.2/S33
60 P4.3/S32
61 P4.4/S31
62 P4.5/S30
63 P4.6/S29
64 P4.7/S28
65 P5.0/S27
66 P5.1/S26
67 P5.2/S25
68 P5.3/S24
69 P5.4/S23
70 P5.5/S22
71 P5.6/S21
72 P5.7/S20
73 P6.0/S19
74 DVSYS
75 DVSS
76
P6.1/S18
77
P6.2/S17
78
P6.3/S16
79
P6.4/S15
80
P6.5/S14
81
P6.6/S13
82
P6.7/S12
83
P7.0/S11
84
P7.1/S10
85
P7.2/S9
86
P7.3/S8
87
P7.4/S7
88
P7.5/S6
89
P7.6/S5
90
P7.7/S4
91
P8.0/S3
92
P8.1/S2
93
P8.2/S1
94
P8.3/S0
95
TEST/SBWTCK
96
PJ.0/SMCLK/TDO
97
PJ.1/MCLK/TDI/TCLK
98
PJ.2/ADC10CLK/TMS
99
PJ.3/ACLK/TCK
100
RST/NMI/SBWTDIO
MSP430F673x
MSP430F672x
www.ti.com SLAS731C –DECEMBER 2011–REVISED FEBRUARY 2013
Pin Designation, MSP430F673xIPZ
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default
mapping. See Table 14 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
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