Datasheet

MSP430F673x
MSP430F672x
SLAS731C –DECEMBER 2011–REVISED FEBRUARY 2013 www.ti.com
Table 56. eUSCI_A1 Registers (Base Address:05E0h) (continued)
REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A interrupt flags UCA1IFG 1Ch
eUSCI_A interrupt vector word UCA1IV 1Eh
Table 57. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA2CTLW0 00h
eUSCI _A control word 1 UCA2CTLW1 02h
eUSCI_A baud rate 0 UCA2BR0 06h
eUSCI_A baud rate 1 UCA2BR1 07h
eUSCI_A modulation control UCA2MCTLW 08h
eUSCI_A status UCA2STAT 0Ah
eUSCI_A receive buffer UCA2RXBUF 0Ch
eUSCI_A transmit buffer UCA2TXBUF 0Eh
eUSCI_A LIN control UCA2ABCTL 10h
eUSCI_A IrDA transmit control UCA2IRTCTL 12h
eUSCI_A IrDA receive control UCA2IRRCTL 13h
eUSCI_A interrupt enable UCA2IE 1Ah
eUSCI_A interrupt flags UCA2IFG 1Ch
eUSCI_A interrupt vector word UCA2IV 1Eh
Table 58. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_B control word 0 UCB0CTLW0 00h
eUSCI_B control word 1 UCB0CTLW1 02h
eUSCI_B bit rate 0 UCB0BR0 06h
eUSCI_B bit rate 1 UCB0BR1 07h
eUSCI_B status word UCB0STATW 08h
eUSCI_B byte counter threshold UCB0TBCNT 0Ah
eUSCI_B receive buffer UCB0RXBUF 0Ch
eUSCI_B transmit buffer UCB0TXBUF 0Eh
eUSCI_B I2C own address 0 UCB0I2COA0 14h
eUSCI_B I2C own address 1 UCB0I2COA1 16h
eUSCI_B I2C own address 2 UCB0I2COA2 18h
eUSCI_B I2C own address 3 UCB0I2COA3 1Ah
eUSCI_B received address UCB0ADDRX 1Ch
eUSCI_B address mask UCB0ADDMASK 1Eh
eUSCI I2C slave address UCB0I2CSA 20h
eUSCI interrupt enable UCB0IE 2Ah
eUSCI interrupt flags UCB0IFG 2Ch
eUSCI interrupt vector word UCB0IV 2Eh
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