Datasheet

P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
Direction
0: Input
1: Output
PySEL.x
1
0
PyDIR.x
PyIN.x
PyIRQ.x
EN
to Port Mapping
1
0
from Port Mapping
PyOUT.x
Interrupt
Edge
Select
Q
EN
Set
PySEL.x
PyIES.x
PyIFG.x
PyIE.x
1
0
DVSS
DVCC
1
PyDS.x
0: Low drive
1: High drive
D
from Port Mapping
COM4 to COM7
from LCD_C
Pad Logic
PyREN.x
PyMAP.x = PMAP_ANALOG
Bus
Keeper
MSP430F673x
MSP430F672x
www.ti.com SLAS731C –DECEMBER 2011–REVISED FEBRUARY 2013
Port P1, P1.6 and P1.7 (MSP430F67xxIPZ and MSP430F67xxIPN),
Port P2, P2.0 and P2.1 (MSP430F67xxIPZ Only) Input/Output With Schmitt Trigger
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