Datasheet

MSP430F673x
MSP430F672x
www.ti.com SLAS731C –DECEMBER 2011–REVISED FEBRUARY 2013
Table 53. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 1 control DMA1CTL 20h
DMA channel 1 source address low DMA1SAL 22h
DMA channel 1 source address high DMA1SAH 24h
DMA channel 1 destination address low DMA1DAL 26h
DMA channel 1 destination address high DMA1DAH 28h
DMA channel 1 transfer size DMA1SZ 2Ah
Table 54. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 2 control DMA2CTL 30h
DMA channel 2 source address low DMA2SAL 32h
DMA channel 2 source address high DMA2SAH 34h
DMA channel 2 destination address low DMA2DAL 36h
DMA channel 2 destination address high DMA2DAH 38h
DMA channel 2 transfer size DMA2SZ 3Ah
Table 55. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA0CTLW0 00h
eUSCI _A control word 1 UCA0CTLW1 02h
eUSCI_A baud rate 0 UCA0BR0 06h
eUSCI_A baud rate 1 UCA0BR1 07h
eUSCI_A modulation control UCA0MCTLW 08h
eUSCI_A status UCA0STAT 0Ah
eUSCI_A receive buffer UCA0RXBUF 0Ch
eUSCI_A transmit buffer UCA0TXBUF 0Eh
eUSCI_A LIN control UCA0ABCTL 10h
eUSCI_A IrDA transmit control UCA0IRTCTL 12h
eUSCI_A IrDA receive control UCA0IRRCTL 13h
eUSCI_A interrupt enable UCA0IE 1Ah
eUSCI_A interrupt flags UCA0IFG 1Ch
eUSCI_A interrupt vector word UCA0IV 1Eh
Table 56. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA1CTLW0 00h
eUSCI _A control word 1 UCA1CTLW1 02h
eUSCI_A baud rate 0 UCA1BR0 06h
eUSCI_A baud rate 1 UCA1BR1 07h
eUSCI_A modulation control UCA1MCTLW 08h
eUSCI_A status UCA1STAT 0Ah
eUSCI_A receive buffer UCA1RXBUF 0Ch
eUSCI_A transmit buffer UCA1TXBUF 0Eh
eUSCI_A LIN control UCA1ABCTL 10h
eUSCI_A IrDA transmit control UCA1IRTCTL 12h
eUSCI_A IrDA receive control UCA1IRRCTL 13h
eUSCI_A interrupt enable UCA1IE 1Ah
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