Datasheet

Unified
Clock
System
128KB
96KB
64KB
32KB
16KB
Flash
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 3+1)
XIN
XOUT
JTAG/
SBW
Interface/
Port PJ
SD24_B
3 Channel
2 Channel
ADC10_A
10 Bit
200 KSPS
LCD_C
8MUX
Up to 320
Segments
REF
Reference
1.5V, 2.0V,
2.5V
DVCC DVSS AVCC AVSS
PA
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
P1.x
P2.x
RST/NMI
TA1
TA2
TA3
Timer_A
2 CC
Registers
8KB
4KB
2KB
1KB
RAM
PJ.x
DMA
3 Channel
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
MPY32
SYS
Watchdog
Port
Mapping
Controller
CRC16
PC
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
P5.x
P6.x
PB
I/O Ports
P3/P4
2×8 I/Os
PB
1×16 I/Os
P3.x
P4.x
RTC_C
(32kHz)
AUX1
AUX2 AUX3
eUSCI_B0
(SPI, I2C)
eUSCI_A0
eUSCI_A1
eUSCI_A2
(UART,
IrDA,SPI)
TA0
Timer_A
3 CC
Registers
Unified
Clock
System
128kB
96KB
64KB
32KB
16KB
Flash
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 3+1)
XIN
XOUT
JTAG/
SBW
Interface/
Port PJ
eUSCI_A0
eUSCI_A1
eUSCI_A2
(UART,
IrDA,SPI)
SD24_B
3 Channel
2 Channel
ADC10_A
10 Bit
200 KSPS
LCD_C
8MUX
Up to 320
Segments
REF
Reference
1.5V, 2.0V,
2.5V
DVCC DVSS AVCC AVSS
PA
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
P1.x
P2.x
RST/NMI
TA0
8kB
4KB
2KB
1KB
RAM
PJ.x
DMA
3 Channel
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
MPY32
SYS
Watchdog
Port
Mapping
Controller
CRC16
P9.x
PD
I/O Ports
P7/P8
2×8 I/Os
PD
1×16 I/Os
I/O Ports
P9
1×4 I/O
PE
1×4 I/O
P7.x
P8.x
PE
PC
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
P5.x
P6.x
PB
I/O Ports
P3/P4
2×8 I/Os
PB
1×16 I/Os
P3.x
P4.x
eUSCI_B0
(SPI, I2C)
RTC_C
(32kHz)
AUX1
AUX2 AUX3
TA1
TA2
TA3
Timer_A
2 CC
Registers
Timer_A
3 CC
Registers
MSP430F673x
MSP430F672x
SLAS731C –DECEMBER 2011–REVISED FEBRUARY 2013 www.ti.com
Functional Block Diagram, MSP430F673xIPZ, MSP430F672xIPZ
Functional Block Diagram, MSP430F673xIPN, MSP430F672xIPN
4 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated