Datasheet

MSP430F673x
MSP430F672x
www.ti.com SLAS731C –DECEMBER 2011–REVISED FEBRUARY 2013
Port Mapping Controller
The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, and P3.
Table 14. Port Mapping Mnemonics and Functions
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
PM_UCA0RXD eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
1
PM_UCA0SOMI eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
PM_UCA0TXD eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
2
PM_UCA0SIMO eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
3 PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI)
4 PM_UCA0STE eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA1RXD eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
5
PM_UCA1SOMI eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
PM_UCA1TXD eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
6
PM_UCA1SIMO eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
7 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)
8 PM_UCA1STE eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA2RXD eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
9
PM_UCA2SOMI eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
PM_UCA2TXD eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
10
PM_ UCA2SIMO eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
11 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI)
12 PM_UCA2STE eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCB0SIMO eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
13
PM_UCB0SDA eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
PM_UCB0SOMI eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
14
PM_UCB0SCL eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
15 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI)
16 PM_UCB0STE eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
17 PM_TA0.0 TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
18 PM_TA0.1 TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
19 PM_TA0.2 TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
20 PM_TA1.0 TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0
21 PM_TA1.1 TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
22 PM_TA2.0 TA2 CCR0 capture input CCI0A TA2 CCR0 compare output Out0
23 PM_TA2.1 TA2 CCR1 capture input CCI1A TA2 CCR1 compare output Out1
24 PM_TA3.0 TA3 CCR0 capture input CCI0A TA3 CCR0 compare output Out0
25 PM_TA3.1 TA3 CCR1 capture input CCI1A TA3 CCR1 compare output Out1
Timer_A clock input to
PM_TACLK None
TA0, TA1, TA2, TA3
26
PM_RTCCLK None RTC_C clock output
27 PM_SDCLK SD24_B bit stream clock input/output (direction controlled by SD24_B)
28 PM_SD0DIO SD24_B converter-0 bit stream data input/output (direction controlled by SD24_B)
29 PM_SD1DIO SD24_B converter-1 bit stream data input/output (direction controlled by SD24_B)
30 PM_SD2DIO SD24_B converter-2 bit stream data input/output (direction controlled by SD24_B)
Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross
31(0FFh)
(1)
PM_ANALOG
currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.
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