Datasheet

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MSP430F673x

MSP430F672x

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SLAS731C –DECEMBER 2011–REVISED FEBRUARY 2013

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 9. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations

SYSTEM WORD

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

INTERRUPT ADDRESS

System Reset

Power-Up

External Reset WDTIFG, KEYV (SYSRSTIV)

(1)(2)

Reset 0FFFEh 63, highest

Watchdog Timeout, Key Violation

Flash Memory Key Violation

System NMI

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

PMM

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62

Vacant Memory Access

JMBOUTIFG (SYSSNIV)

(1)(3)

JTAG Mailbox

User NMI

NMI

NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG

Oscillator Fault (Non)maskable 0FFFAh 61

(SYSUNIV)

(1)(3)

Flash Memory Access Violation

Supply Switch

Watchdog Timer_A Interval Timer

WDTIFG Maskable 0FFF8h 60

Mode

eUSCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)

(1)(4)

Maskable 0FFF6h 59

eUSCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)

(1)(4)

Maskable 0FFF4h 58

ADC10IFG0, ADC10INIFG, ADC10LOIFG,

ADC10_A ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG Maskable 0FFF2h 57

(ADC10IV)

(1)(4)

SD24_B SD24_B Interrupt Flags (SD24IV)

(1)(4)

Maskable 0FFF0h 56

Timer TA0 TA0CCR0 CCIFG0

(4)

Maskable 0FFEEh 55

TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,

Timer TA0 Maskable 0FFECh 54

TA0IFG (TA0IV)

(1)(4)

eUSCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)

(1)(4)

Maskable 0FFEAh 53

eUSCI_A2 Receive or Transmit UCA2RXIFG, UCA2TXIFG (UCA2IV)

(1)(4)

Maskable 0FFE8h 52

Auxiliary Supplies Auxiliary Supplies Interrupt Flags (AUXIV)

(1)(4)

Maskable 0FFE6h 51

DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)

(1)(4)

Maskable 0FFE4h 50

Timer TA1 TA1CCR0 CCIFG0

(4)

Maskable 0FFE2h 49

TA1CCR1 CCIFG1,

Timer TA1 Maskable 0FFE0h 48

TA1IFG (TA1IV)

(1)(4)

I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)

(1)(4)

Maskable 0FFDEh 47

Timer TA2 TA2CCR0 CCIFG0

(4)

Maskable 0FFDCh 46

TA2CCR1 CCIFG1,

Timer TA2 Maskable 0FFDAh 45

TA2IFG (TA2IV)

(1)(4)

I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)

(1)(4)

Maskable 0FFD8h 44

Timer TA3 TA3CCR0 CCIFG0

(4)

Maskable 0FFD6h 43

TA3CCR1 CCIFG1,

Timer TA3 Maskable 0FFD4h 42

TA3IFG (TA3IV)

(1)(4)

LCD_C LCD_C Interrupt Flags (LCDCIV)

(1)(4)

Maskable 0FFD2h 41

RTCOFIFG, RTCRDYIFG, RTCTEVIFG,

RTC_C Maskable 0FFD0h 40

RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)

(1)(4)

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(4) Interrupt flags are located in the module.