Datasheet

MSP430F673x
MSP430F672x
www.ti.com SLAS731C –DECEMBER 2011–REVISED FEBRUARY 2013
Table 6. Terminal Functions, MSP430F67xxIPN (continued)
TERMINAL
NO. I/O
(1)
DESCRIPTION
NAME
PN
General-purpose digital I/O
P5.0/S15 57 I/O
LCD segment output S15
General-purpose digital I/O
P5.1/S14 58 I/O
LCD segment output S14
DVSYS
(5)
59 Digital power supply for I/Os
DVSS 60 Digital ground supply
General-purpose digital I/O
P5.2/S13 61 I/O
LCD segment output S13
General-purpose digital I/O
P5.3/S12 62 I/O
LCD segment output S12
General-purpose digital I/O
P5.4/S11 63 I/O
LCD segment output S11
General-purpose digital I/O
P5.5/S10 64 I/O
LCD segment output S10
General-purpose digital I/O
P5.6/S9 65 I/O
LCD segment output S9
General-purpose digital I/O
P5.7/S8 66 I/O
LCD segment output S8
General-purpose digital I/O
P6.0/S7 67 I/O
LCD segment output S7
General-purpose digital I/O
P6.1/S6 68 I/O
LCD segment output S6
General-purpose digital I/O
P6.2/S5 69 I/O
LCD segment output S5
General-purpose digital I/O
P6.3/S4 70 I/O
LCD segment output S4
General-purpose digital I/O
P6.4/S3 71 I/O
LCD segment output S3
General-purpose digital I/O
P6.5/S2 72 I/O
LCD segment output S2
General-purpose digital I/O
P6.6/S1 73 I/O
LCD segment output S1
General-purpose digital I/O
P6.7/S0 74 I/O
LCD segment output S0
Test mode pin – select digital I/O on JTAG pins
TEST/SBWTCK 75 I
Spy-Bi-Wire input clock
General-purpose digital I/O
PJ.0/SMCLK/TDO 76 I/O
SMCLK clock output
Test data output
General-purpose digital I/O
PJ.1/MCLK/TDI/TCLK 77 I/O
MCLK clock output
Test data input or Test clock input
(5) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
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