Datasheet

R = 3 k
Load
W
AV
CC
C = 100 pF
Load
2
DAC Output
R
O/P(DAC12.x)
I
Load
Conversion 1 Conversion 2
V
OUT
Conversion 3
Glitch
Energy
±1/2 LSB
±1/2 LSB
t
settleLH
t
settleHL
MSP430F6638, MSP430F6637, MSP430F6636
MSP430F6635, MSP430F6634, MSP430F6633
MSP430F6632, MSP430F6631, MSP430F6630
www.ti.com SLAS566D –JUNE 2010–REVISED AUGUST 2013
12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
AV
CC
AV
CC
DAC12IR = 0
(1) (2)
/ 3 + 0.2
Reference input voltage
VeREF+ 2.2 V, 3 V V
range
AV
CC
DAC12IR = 1
(3) (4)
AV
CC
+ 0.2
DAC12_0 IR = DAC12_1 IR = 0 20 MΩ
DAC12_0 IR = 1, DAC12_1 IR = 0 48
Ri
(VREF+)
,
Reference input resistance
(5)
2.2 V, 3 V
DAC12_0 IR = 0, DAC12_1 IR = 1 48
Ri
(VeREF+)
kΩ
DAC12_0 IR = DAC12_1 IR = 1,
24
DAC12_0 SREFx = DAC12_1 SREFx
(6)
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AV
CC
– V
E(O)
] / [3 × (1 + E
G
)].
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AV
CC
– V
E(O)
] / (1 + E
G
).
(5) This impedance depends on tradeoff in power savings. Current devices have 48 kΩ for each channel when divide is enabled. Can be
increased if performance can be maintained.
(6) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-Bit DAC, Dynamic Specifications
V
REF
= V
CC
, DAC12IR = 1 (see Figure 20 and Figure 21), over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
DAC12AMPx = 0 → {2, 3, 4} 60 120
DAC12_xDAT = 800h,
t
ON
DAC12 on time Error
V(O)
< ± 0.5 LSB
(1)
DAC12AMPx = 0 → {5, 6} 2.2 V, 3 V 15 30 µs
(see Figure 20)
DAC12AMPx = 0 → 7 6 12
DAC12AMPx = 2 100 200
DAC12_xDAT =
t
S(FS)
Settling time, full scale DAC12AMPx = 3, 5 2.2 V, 3 V 40 80 µs
80h → F7Fh → 80h
DAC12AMPx = 4, 6, 7 15 30
DAC12AMPx = 2 5
DAC12_xDAT =
Settling time, code to
t
S(C-C)
3F8h → 408h → 3F8h, DAC12AMPx = 3, 5 2.2 V, 3 V 2 µs
code
BF8h → C08h → BF8h
DAC12AMPx = 4, 6, 7 1
DAC12AMPx = 2 0.05 0.35
DAC12_xDAT =
SR Slew rate DAC12AMPx = 3, 5 2.2 V, 3 V 0.35 1.10 V/µs
80h → F7Fh → 80h
(2)
DAC12AMPx = 4, 6, 7 1.50 5.20
DAC12_xDAT =
Glitch energy DAC12AMPx = 7 2.2 V, 3 V 35 nV-s
800h → 7FFh → 800h
(1) R
Load
and C
Load
connected to AV
SS
(not AV
CC
/2) in Figure 20.
(2) Slew rate applies to output voltage steps ≥ 200 mV.
Figure 20. Settling Time and Glitch Energy Testing
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