Datasheet
MSP430F6638, MSP430F6637, MSP430F6636
MSP430F6635, MSP430F6634, MSP430F6633
MSP430F6632, MSP430F6631, MSP430F6630
SLAS566D –JUNE 2010–REVISED AUGUST 2013
www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at V
CC
to V
SS
–0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE, VBUS, V18)
(2)
–0.3 V to V
CC
+ 0.3 V
Diode current at any device pin ±2 mA
Storage temperature range, T
stg
(3)
–55°C to 150°C
Maximum junction temperature, T
J
95°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
. VCORE is for internal device use only. No external dc loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics
PARAMETER VALUE UNIT
QFP (PZ) 122
θ
JA
Junction-to-ambient thermal resistance, still air
(1)
°C/W
BGA (ZQW) 108
QFP (PZ) 83
θ
JC(TOP)
Junction-to-case (top) thermal resistance
(2)
°C/W
BGA (ZQW) 72
QFP (PZ) 98
θ
JB
Junction-to-board thermal resistance
(3)
°C/W
BGA (ZQW) 76
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
Recommended Operating Conditions
MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6
Supply voltage during program execution and flash
PMMCOREVx = 0, 1 2.0 3.6
V
CC
programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 = V
PMMCOREVx = 0, 1, 2 2.2 3.6
DV
CC
= V
CC
)
(1)(2)
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
PMMCOREVx = 0 1.8 3.6
PMMCOREVx = 0, 1 2.0 3.6
Supply voltage during USB operation, USB PLL disabled
(USB_EN = 1, UPLLEN = 0)
PMMCOREVx = 0, 1, 2 2.2 3.6
V
CC,USB
V
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
PMMCOREVx = 2 2.2 3.6
Supply voltage during USB operation, USB PLL enabled
(3)
(USB_EN = 1, UPLLEN = 1)
PMMCOREVx = 2, 3 2.4 3.6
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =
V
SS
0 V
DVSS2 = DVSS3 = V
SS
)
T
A
= 0°C to 85°C 1.55 3.6
V
BAT,RTC
Backup-supply voltage with RTC operational V
T
A
= –40°C to 85°C 1.70 3.6
V
BAT,MEM
Backup-supply voltage with backup memory retained. T
A
= –40°C to 85°C 1.20 3.6 V
T
A
Operating free-air temperature I version –40 85 °C
T
J
Operating junction temperature I version –40 85 °C
C
BAK
Capacitance at pin VBAK 1 4.7 10 nF
(1) It is recommended to power AV
CC
and DV
CC
from the same source. A maximum difference of 0.3 V between AV
CC
and DV
CC
can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(3) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.
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