Datasheet

MSP430F6438, MSP430F6436
MSP430F6435, MSP430F6433
SLAS720C –AUGUST 2010–REVISED AUGUST 2013 www.ti.com
Table 41. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTION REGISTER OFFSET
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control register 0 MPY32CTL0 2Ch
Table 42. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTION REGISTER OFFSET
DMA General Control: DMA module control 0 DMACTL0 00h
DMA General Control: DMA module control 1 DMACTL1 02h
DMA General Control: DMA module control 2 DMACTL2 04h
DMA General Control: DMA module control 3 DMACTL3 06h
DMA General Control: DMA module control 4 DMACTL4 08h
DMA General Control: DMA interrupt vector DMAIV 0Ah
DMA Channel 0 control DMA0CTL 00h
DMA Channel 0 source address low DMA0SAL 02h
DMA Channel 0 source address high DMA0SAH 04h
DMA Channel 0 destination address low DMA0DAL 06h
DMA Channel 0 destination address high DMA0DAH 08h
DMA Channel 0 transfer size DMA0SZ 0Ah
DMA Channel 1 control DMA1CTL 00h
DMA Channel 1 source address low DMA1SAL 02h
DMA Channel 1 source address high DMA1SAH 04h
DMA Channel 1 destination address low DMA1DAL 06h
DMA Channel 1 destination address high DMA1DAH 08h
DMA Channel 1 transfer size DMA1SZ 0Ah
DMA Channel 2 control DMA2CTL 00h
DMA Channel 2 source address low DMA2SAL 02h
DMA Channel 2 source address high DMA2SAH 04h
DMA Channel 2 destination address low DMA2DAL 06h
DMA Channel 2 destination address high DMA2DAH 08h
DMA Channel 2 transfer size DMA2SZ 0Ah
DMA Channel 3 control DMA3CTL 00h
DMA Channel 3 source address low DMA3SAL 02h
DMA Channel 3 source address high DMA3SAH 04h
DMA Channel 3 destination address low DMA3DAL 06h
DMA Channel 3 destination address high DMA3DAH 08h
DMA Channel 3 transfer size DMA3SZ 0Ah
DMA Channel 4 control DMA4CTL 00h
DMA Channel 4 source address low DMA4SAL 02h
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