Datasheet

MSP430F6438, MSP430F6436
MSP430F6435, MSP430F6433
SLAS720C –AUGUST 2010–REVISED AUGUST 2013 www.ti.com
Table 10. Port Mapping, Mnemonics and Functions (continued)
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
PM_CBOUT - Comparator_B output
1
PM_TB0CLK Timer TB0 clock input -
PM_ADC12CLK - ADC12CLK
2
PM_DMAE0 DMAE0 Input -
PM_SVMOUT - SVM output
3
Timer TB0 high impedance input
PM_TB0OUTH -
TB0OUTH
4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0
5 PM_TB0CCR1B Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1
6 PM_TB0CCR2B Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2
7 PM_TB0CCR3B Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3
8 PM_TB0CCR4B Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4
9 PM_TB0CCR5B Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5
10 PM_TB0CCR6B Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6
PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input)
11
PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output)
12
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
13
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
14
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
15
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
16
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
17 PM_MCLK - MCLK
18 Reserved Reserved for test purposes. Do not use this setting.
19 Reserved Reserved for test purposes. Do not use this setting.
20-30 Reserved None DVSS
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
31 (0FFh)
(1)
PM_ANALOG
when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
which results in a read out value of 31.
Table 11. Default Mapping
PxMAPy
PIN INPUT PIN FUNCTION OUTPUT PIN FUNCTION
MNEMONIC
PM_UCB0STE, USCI_B0 SPI slave transmit enable (direction controlled by USCI - input),
P2.0/P2MAP0
PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0SIMO, USCI_B0 SPI slave in master out (direction controlled by USCI),
P2.1/P2MAP1
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0SOMI, USCI_B0 SPI slave out master in (direction controlled by USCI),
P2.2/P2MAP2
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0CLK, USCI_B0 clock input/output (direction controlled by USCI),
P2.3/P2MAP3
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
PM_UCA0TXD, USCI_A0 UART TXD (direction controlled by USCI - output),
P2.4/P2MAP4
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0RXD, USCI_A0 UART RXD (direction controlled by USCI - input),
P2.5/P2MAP5
PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
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