Datasheet

MSP430F6438, MSP430F6436
MSP430F6435, MSP430F6433
www.ti.com SLAS720C –AUGUST 2010–REVISED AUGUST 2013
Table 9. Spy-Bi-Wire Pin Requirements and Functions (continued)
DEVICE SIGNAL DIRECTION FUNCTION
VSS Ground supply
Flash Memory (Link to User's Guide)
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A can be locked separately.
RAM Memory (Link to User's Guide)
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in Memory Organization.
• Each sector 0 to n can be complete disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
Backup RAM Memory
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during
operation from a backup supply if the Battery Backup System module is implemented.
There are 8 bytes of Backup RAM available on MSP430F643x. It can be wordwise accessed via the control
registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
Digital I/O (Link to User's Guide)
There are up to nine 8-bit I/O ports implemented: P1 through P6, P8, and P9 are complete, P7 contains six
individual I/O ports, and PJ contains four individual I/O ports.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).
Port Mapping Controller (Link to User's Guide)
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.
Table 10. Port Mapping, Mnemonics and Functions
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DV
SS
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